Cypress Semiconductor CY7C138 Ficha de especificações - Página 8

Procurar online ou descarregar pdf Ficha de especificações para Hardware informático Cypress Semiconductor CY7C138. Cypress Semiconductor CY7C138 18 páginas. 4k x 8/9 dual-port static ram with sem, int, busy

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Switching Waveforms
ADDRESS
SEM OR CE
R/W
DATA IN
OE
DATA OUT
Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)
ADDRESS
SEM OR CE
R/W
DATA IN
DATA OUT
Notes
20. BUSY = HIGH for the writing port.
21. CE
= CE
= LOW.
L
R
22. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and
either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that
terminates the write.
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
and data to be placed on the bus for the required t
apply and the write pulse can be as short as the specified t
24. R/W must be HIGH during all address transitions.
Document #: 38-06037 Rev. *D
(continued)
t
SCE
t
AW
t
SA
t
HZOE

HIGH IMPEDANCE

t
WC
t
SCE
t
AW
t
SA
t
HZWE
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not
SD
.
PWE
Figure 8. Semaphore Read After Write Timing, Either Side
t
WC
t
PWE
t
SD
DATA VALID
t
PWE
t
t
SD
HD
DATA VALID
HIGH IMPEDANCE
or (t
+ t
PWE
HZWE
SD
CY7C138, CY7C139
t
HA
t
HD
t
LZOE
[22, 24, 25]
t
HA
t
LZWE
) to allow the I/O drivers to turn off
[26]
Page 8 of 17
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