Cypress Semiconductor MoBL-USB CY7C68000A Ficha de especificações - Página 10

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AC Electrical Characteristics

USB 2.0 Transceiver
USB 2.0-compliant in FS and HS modes.
Timing Diagram
HS/FS Interface Timing - 60 MHz
CLK
Control_In
DataIn
Control_Out
DataOut
Table 3. 60 MHz Interface Timing Constraints Parameters
Parameter
T
Minimum setup time for TXValid
CSU_MIN
T
Minimum hold time for TXValid
CH_MIN
T
Minimum setup time for Data (transmit direction)
DSU_MIN
T
Minimum hold time for Data (transmit direction)
DH_MIN
T
Clock to Control out time for TXReady, RXValid,
CCO
RXActive and RXError
T
Clock to Data out time (Receive direction)
CDO
Document #: 38-08052 Rev. *G
Figure 3. 60 MHz Interface Timing Constraints
TCH_MIN
TCSU_MIN
TDH_MIN
TDSU_MIN
Description
TCCO
TCDO
Min
Typ
Max
4
1
4
1
1
8
1
8
CY7C68000A
Unit
Notes
ns
ns
ns
ns
ns
ns
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