Cypress Semiconductor STK14C88-3 Ficha de especificações - Página 4

Procurar online ou descarregar pdf Ficha de especificações para Hardware informático Cypress Semiconductor STK14C88-3. Cypress Semiconductor STK14C88-3 18 páginas. 256 kbit (32k x 8) autostore nvsram

Imprimir página

Figure 3. AutoStore Inhibit Mode

Hardware STORE (HSB) Operation

The STK14C88-3 provides the HSB pin for controlling and

acknowledging the STORE operations. The HSB pin is used

to request a hardware STORE cycle. When the HSB pin is

driven LOW, the STK14C88-3 conditionally initiates a STORE

operation after t

. An actual STORE cycle only begins if a

DELAY

WRITE to the SRAM takes place since the last STORE or

RECALL cycle. The HSB pin also acts as an open drain driver

that is internally driven LOW to indicate a busy condition, while

the STORE (initiated by any means) is in progress. Pull up this

pin with an external 10K ohm resistor to V

as a driver.

SRAM READ and WRITE operations, that are in progress

when HSB is driven LOW by any means, are given time to

complete before the STORE operation is initiated. After HSB

goes LOW, the STK14C88-3 continues SRAM operations for

. During t

, multiple SRAM READ operations take

DELAY

place. If a WRITE is in progress when HSB is pulled LOW, it

allows a time, t

to complete. However, any SRAM

DELAY

WRITE cycles requested after HSB goes LOW are inhibited

until HSB returns HIGH.

The HSB pin is used to synchronize multiple STK14C88-3

while using a single larger capacitor. To operate in this mode,

the HSB pin is connected together to the HSB pins from the

other STK14C88-3. An external pull up resistor to V

required, since HSB acts as an open drain pull down. The

pins from the other STK14C88-3 parts are tied together

CAP

Document Number: 001-50592 Rev. **

and share a single capacitor. The capacitor size is scaled by

the number of devices connected to it. When any one of the

STK14C88-3 detects a power loss and asserts HSB, the

common HSB pin causes all parts to request a STORE cycle.

(A STORE takes place in those STK14C88-3 that are written

since the last nonvolatile cycle.)

During any STORE operation, regardless of how it is initiated,

the STK14C88-3 continues to drive the HSB pin LOW,

releasing it only when the STORE is complete. After

completing the STORE operation, the STK14C88-3 remains

disabled until the HSB pin returns HIGH.

If HSB is not used, it is left unconnected.

Hardware RECALL (Power Up)

During power up or after any low power condition (V

RESET

once again exceeds the sense voltage of V

cycle is automatically initiated and takes t

If the STK14C88-3 is in a WRITE state at the end of power up

RECALL, the SRAM data is corrupted. To help avoid this

situation, a 10 Kohm resistor is connected either between WE

and system V

Software STORE

Data is transferred from the SRAM to the nonvolatile memory

by a software address sequence. The STK14C88-3 software

STORE cycle is initiated by executing sequential CE controlled

READ cycles from six specific address locations in exact

order. During the STORE cycle, an erase of the previous

nonvolatile data is first performed followed by a program of the

nonvolatile elements. When a STORE cycle is initiated, input

and output are disabled until the cycle is completed.

Because a sequence of READs from specific addresses is

used for STORE initiation, it is important that no other READ

or WRITE accesses intervene in the sequence. If they

intervene, the sequence is aborted and no STORE or RECALL

takes place.

if HSB is used

To initiate the software STORE cycle, the following READ

CAP

sequence is performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0FC0, Initiate STORE cycle

The software sequence is clocked with CE controlled READs.

When the sixth address in the sequence is entered, the

STORE cycle commences and the chip is disabled. It is

important that READ cycles and not WRITE cycles are used

in the sequence. It is not necessary that OE is LOW for a valid

CAP

sequence. After the t

again activated for READ and WRITE operation.

), an internal RECALL request is latched. When V

or between CE and system V

cycle time is fulfilled, the SRAM is

STORE

STK14C88-3

, a RECALL

SWITCH

to complete.

HRECALL

Page 4 of 17

[+] Feedback