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AD484 user manual
Figure 4: switch (J1) location
Sw1
OFF
Default setting. The Virtex-4 device A configuration is loaded from the flash at
power up.
ON
Virtex-4 device A safety configuration loaded from the flash at power up. To be
used only if the Virtex-4 device A cannot be configured or does not perform
properly with the switch in the OFF position.
Sw2
Reserved
Sw3
Reserved
Sw4
Reserved
Table 3: Switch description
3.2.2.2
LED and board status
Four LEDs connect to the CPLD and give information about the board status.
LED 0
Flashing
ON
OFF
LED 1
Flashing
ON
OFF
LED 2
Flashing
ON
OFF
LED 3
ON
LED 3
OFF
Table 4: LED board status
February 2007
FPGA A or B bitstream or user_ROM_register is currently
being written to the flash
FPGA A not configured
FPGA A configured
FPGA A or B bitstream or user_ROM_register is currently
being written to the flash
FPGA B not configured
FPGA B configured
The Virtex-4 device A has been configured with the safety
configuration bitstream programmed in the flash at factory.
Please write a valid Virtex-4 device A bitstream to the flash.
Flash is busy writing or erasing
Flash device is not busy
CRC error. Presumably a wrong or corrupted FPGA bitstream
has been written to the flash. Once on this LED remains on
No CRC error detected
AD484 User manual
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