4DSP FMC150 Руководство пользователя - Страница 9
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4.2.1 EEPROM
The FMC150 card carries a small serial EEPROM (24LC02B) which is accessible from the
carrier card through the I
is only 0.01µA when SCL and SDA are kept at 3V3VAUX level. The EEPROM is write-
protected. The protection can be removed by switching on SW1 of the DIP switch (silk screen
label is "WR EN").
4.2.1 JTAG
The FMC150 card TDO pin is connected to the TDI pin to ensure continuity of the JTAG chain.
TCK, TMS and TRST are left unconnected on the FMC150.
4.2.2 FMC Connector
The low-pin count connector has only bank LA available and two dedicated LVDS clock pairs.
The recommendations from AV57.1 Table 14 have been taking into account resulting in the
following arrangement:
The clock and data pairs from the ADC are mapped to LA00_CC and LA01-LA14
respectively.
The remaining connections from this associated I/O signals (LA15-LA16) are used for
non-critical control signals.
The reference clock for the DAC interface is mapped to CLK0_M2C. The clock, frame,
and data pairs to the DAC are mapped to LA17-LA26.
The remaining connections from this associated I/O signals (LA27-LA33) are used for
non-critical control signals.
The external trigger connects to CLK1_M2C.
Refer also to Appendix A. LPC pin-out.
4.3 Main characteristics
Number of channels
Channel resolution
Input voltage range
Input gain
Input impedance
Analogue input bandwidth
SNR
SFDR
January 2012
2
C bus. The EEPROM is powered by 3V3VAUX. The standby current
Analog Inputs
2
14-bit
2Vp-p (10 dBm)
Programmable from 0dB to 6dB in 0.5dB steps
(6dB gain gives an input voltage range of 1Vp-p)
50Ω (AC coupled)
0.40-500MHz
71dBFS @ 45MHz Fin
80dBc @ 45MHz Fin
Analog Outputs
FMC150 User Manual
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