Fujitsu D2952 Техническое руководство - Страница 17

Просмотреть онлайн или скачать pdf Техническое руководство для Материнская плата Fujitsu D2952. Fujitsu D2952 38 страниц. For bx924 s2

Features

3.1

Processors

– 2 Intel

Xeon

– 2 processor sockets LGA1366 for Intel

– Integrated memory controller (DDR3)

– 32 KB L1 cache (on-die data cache per core)

– 32 KB L1 cache (on-die instruction cache per core)

– 256 KB L2 cache (mid-level per core)

– Up to 12 MB on chip shared L3 cache (among all cores)

– 2x Intel

QuickPath Interconnect with up to 6,4 GT/s in each direction

Main memory

– 18 slots for main memory DDR3 1066 / 1333 single-, dual- or quad-ranked

DIMM memory modules with 2 GB, 4 GB, 8 GB and 16 GB

– Buffered and unbuffered DIMMs with ECC are supported, mix of memory is

not permitted

– Maximum 288 GB of memory

– Minimum 4 GB (1 memory module / CPU)

– Maximum 32 Gbit/s band width (DDR3)

– Each CPU has 3 DIMM slots per channel

– ECC multiple-bit error detection and single-bit error correction

– Memory scrubbing functionality

– Single Device Data Correction (SDDC) function (Chipkill™)

Chips on the system board

– Intel

5520 chipset

– Intel

ICH10 Base

– 1x dual-port 10 GbE Lan controller Intel

– Two SATA ports for SSD

– TPM 1.2 Infineon SLB9635 TT1.2 card (option)

– Board Management controller iRMC S2 with integrated graphic controller

– 2 MB Flash ROM

– 32Mx16-667 DDR2 SRAM for iRMC S2

– ADT7462 temperature/system monitoring controller

D2952 (BX924 S2)

processors of the 5500 and 5600 series

Technical Manual

Xeon

processors

Niantic