DG USB3D-IP Руководство - Страница 6
Просмотреть онлайн или скачать pdf Руководство для Материнская плата DG USB3D-IP. DG USB3D-IP 16 страниц. Usb3.0 device function ip-core
Печатать страницу
dg_usb3.0_dev_ip_demo_instruction_en.doc
After sof-file download finish and JTAG UART operation start, check USER_LED0-3 status near by
•
HSMC connector on the Altera board. See Table 1 for LED definition. Note that LED0 blinks and
other LEDs are OFF when USB cable is unplugged. When USB cable is connected again, LED will
change its state as shown in Figure 8.
LED
LED
Statu
Statu
LED
LED
Statu
Statu
s s s s
LED0
OFF
Blink
ON
LED1
OFF
ON
LED2
OFF
ON
LED3
OFF
ON
Figure 8 8 8 8 : USB3.0 dev
Figure
Figure
Figure
※ All LED will be OFF when 1-hour time limitation is expired.
15 May 2015
Altera FPGA configuration is not completed.
VBUS is not detected. USB cable is not plugged correctly for example.
USB cable is plugged correctly and FPGA detects VBUS presence.
USB3.0 Mass Storage Class operation is not started yet.
Altera board might have problem such as memory initialization fail.
USB3.0 Mass Storage Class operation is started successfully.
Cannot initialize USB3.0 LINK process.
Check HSMC connection of the demo board.
Check that USB3.0 cable is the demo board attached cable.
USB3.0 LINK initialization completed successfully.
USB3.0 Mass Storage Class detection by HostPC is not completed.
It is possible that signal quality problem exists in the host USB3.0 adapter or
device driver has some problem.
USB3.0 Mass Storage Class detection by HostPC is completed successfully.
Table 1 1 1 1 : LED definition of Altera board
Table
Table
Table
: LED definition of Altera board
: LED definition of Altera board
: LED definition of Altera board
: USB3.0 device operation LED
ice operation LED0 0 0 0 - - - - LED3
: USB3.0 dev
: USB3.0 dev
ice operation LED
ice operation LED
Description
Description
Description
Description
LED3 status on
status on Altera
Altera board
LED3
LED3
status on
status on
Altera
Altera
board
board
board
Page 6