Dell PowerVault LTO4-120 Руководство пользователя - Страница 10
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adaptive Finite Impulse Response (FIR) filters that modify the equalization of each read channel dynamically to compensate for many of those changes.
The error rate of the PowerVault LTO-4-120 Half-Height tape drive is less than 1 hard error in 10
Error-correction Code (ECC)
The use of Cyclic Redundancy Checking (CRC) and two-level orthogonal Error Correction Coding (ECC) provides a very low probability of encountering a hard
error. During the read process, ECC correction is performed on the fly without affecting tape streaming.
There are two levels of Error Correction Coding (ECC). These two levels are orthogonal - that is, an ECC codeword at one level intersects ECC codewords at
the other level just once, which means there will be only one common symbol between them. The two levels are called C1 and C2.
C1 ECC
As data is written to memory from the data processing unit, the DMA/ECC interface generates C1 ECC bytes and writes them to memory.
As data is written to tape, the C1 ECC is checked and an interrupt generated if there is an error. The C1 ECC read from memory is the ECC that is written to
tape.
When data is read from tape and stored into memory, C1 ECC is checked and:
If the C1 ECC is good, the valid bit for the codeword pair is set.
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Otherwise, a pointer to the invalid codeword pair is passed to the C1 ECC correction engine.
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If the C1 ECC correction engine can correct the error, then the corrected bytes are written to memory, and the valid bit is set.
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Otherwise, the valid bit is left cleared.
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As data is read from memory to the data processor for decompression, the C1 ECC is again checked and an interrupt generated if it is not correct.
C2 ECC
C2 ECC involves three distinct operations:
1. Encoding: Generating C2 ECC bytes from data bytes (performed by ECC coprocessor hardware).
2. Decoding: Generating ECC syndromes from data and ECC bytes, testing for all-zeroes (performed by ECC coprocessor hardware).
3. Correction: Generating corrected data from syndromes.
The correction depends on the number and types of errors involved:
For one known C1 codeword pair in error in a subdata set (C2 codeword), the operation is performed by the ECC coprocessor hardware.
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For two or more known C1 codeword pairs in error, the matrix is computed by firmware and the correction is performed by hardware.
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For one or more unknown C1 codeword pairs, syndromes are generated by hardware, error location is computed by firmware, the matrix is computed
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by firmware and the correction is performed by hardware.
Servo-tracking Faults
During a write operation, if the servo system detects an error that may result in adjacent data tracks being overwritten, the write operation is aborted. The
write operation will not continue until the correct servo tracking is re-established.
Data Compression
Typical data streams of text, graphics, software code, or other forms of data contain repeated information either at the text level where you can readily
recognize regular repetitions of a single word, or at the binary level where the repetitions are in bits or bytes. Although most data is unique and random, the
binary level data exhibits patterns of various sizes that repeat with varying degrees of regularity.
Data compression technology reduces or eliminates data redundancy before recording the information to tape. This increases the amount of data that can be
stored on a finite medium and increases the overall storage efficiency of the system.
With data compression, the redundant information in a data stream is identified and represented by codewords or symbols that allow the same data to be
recorded in a fewer number of bits. These codewords or symbols point back to the original data string, using fewer characters to represent the strings.
Because these smaller symbols are substituted for the longer strings of data, more data can be stored in the same physical space.
Some important benefits result from data compression in tape drives:
More data can be stored on a given length of tape.
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Performance can more closely parallel to that of high-transfer-rate computers.
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More information can be transferred in the same time interval.
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1 7
bits. The undetectable error rate is 1 in 10
2 7
bits read.