Diamond Guitar Pedals MEMORY LANE Руководство пользователя - Страница 12

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Technology
Each Memory Lane uses two Panasonic/Matsushita MN3005 4096-stage
bucket brigade devices. These devices have been used in several well-known
analog delays over the years, and when coupled with an NE570 compandor
to reduce noise from the total 8192 sample and hold stages, produce a very
warm echo signal.
Bucket-brigade devices are designed as an integrated chain of sample-and-
hold circuits – essentially a series of capacitors that have their charge passed
on each clock cycle to the next capacitor in the chain. The 'buckets' are the
MOS capacitors that temporarily store the signal charge and the 'brigade'
the clock/shift mechanism that moves those charges from one capacitor to
the next. One interesting note is that analog delays still share one major
characteristic of digital delays – they are still a 'sampled' system bound by
the Nyquist sampling theorem. This requires that sampling be done at least
twice the frequency of the highest frequency in the sampled signal in order to
prevent aliasing artifacts. To prevent aliasing in the Memory Lane, 5th order
Butterworth filters are used both for anti-aliasing before sampling and for
signal reconstruction after the bucket brigades. This requirement for signal
filtering results in a classic engineering tradeoff between total delay time
and the highest frequency passed through the delay system. Thus, the dark
repeats typically associated with analog delays are not so much a product
of the thousands of leaky capacitors in the delay chips but of the steep low
pass filtering required to prevent aliasing while attempting to achieve as long
a delay time as possible. A conceptual diagram of a bucket brigade device is
shown below:
1
The figure below shows a simplified functional block diagram of the Memory
Lane, showing direct and delay signal paths as well as the position of the feed-
back insert point. The true bypass signal path is not shown for clarity.
Direct path
Input
Delay Path
BUFFER
SUMMER
True bypass path
and switching is
external to this
diagram and not
shown for clarity
2
3
Bucket Brigade analog delay line using a series of
clocked sample and hold circuits
Memory Lane Simplified Functional Block Diagram
DELAY
Feedback Level
Receive
4
MODULATION
EQ
Auto FX loop
switching
FX loop
Send
- 12 -
4096
Mix / Direct
SUMMER
Auto stereo
switching
Delay Only
Mix
BUFFER
Output
Output