Digilent Atlys Справочное руководство - Страница 11
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and one reserved (RES) pin. Of these, only the differential data channels and I2C bus are connected
to the FPGA. All signal connections are shown in the table below.
Pin/Signal
1: D2+
2: D2_S
3: D2-
4: D1+
5: D1_S
6: D1-
7: D0+
8: D0_S
9: D0-
10: Clk+
11: Clk_S
12: Clk-
13: CEC
14: RES
15: SCL
16: SDA
17: Gnd
18: 5V
19: HPD
*jumper can disconnect Vdd
Doc: 502-178
HDMI Type A Connectors
J1: IN
J2: Out
B12
B8
GND
GND
A12
A8
B11
C7
GND
GND
A11
A7
G9
D8
GND
GND
F9
C8
D11
B6
GND
GND
C11
A6
NC
0K to Gnd
NC
NC
C13
D9
A13
C9
GND
GND
JP4*
5V
1K to 5V
NC
**shared with J1 I2C signals via jumper JP2
HDMI Type D
J3: IN
Pin/Signal JA: BiDi
J16
1: HPD
GND
2: RES
J18
3: D2+
L17
4: D2_S
GND
5: D2-
L18
6: D1+
K17
7: D1_S
8: D1-
GND
K18
9: D0+
H17
10: D0_S
11: D0-
GND
H18
12: Clk+
NC
13: Clk_S
14: Clk-
NC
M16
15: CEC
M18
16: Gnd
GND
17: SCL
*
18: SCA
JP8
1K to 5V
19: 5V
*
JP3
VCCB2
N5
GND
P6
T4
GND
V4
R3
GND
T3
T9
GND
V9
VCCB2
GND
C13**
A13**
JP3
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