Toshiba TLP510E Руководство по техническому обучению - Страница 24
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Печатать страницу6-2. Each IC Description
6-2-1. PLL IC CXA3106Q (QX028) for RGB Signals
A configuration of CXA3106Q is shown in Fig. 6-2-1.
The PLL IC of CXA3106Q is an IC with high perfor-
mance and low jitter, and can generate the clock signal
synchronized with the horizontal sync signal of max. 120
MHz.
VCO
TTLIN
(TTL)
VCO
PECLIN
(PECL)
SYNC
TTLIN
(TTL)
POLARITY
SYNC
PECLIN
(PECL)
1 bit
HOLD
TTLIN
(TTL)
DAC
CONTROL REGISTER
1 REF
SENABLE
SCLK
RC 1
RC 2
1/16
20/16 CLK
PHASE
CHARGE
FINE
DETECTOR
PUMP
DELAY
1 bit
2 bits
5 bits
1/256
1/4096
PROGRAMMABLE
COUNTER
12 bits
1 bit
1 bit
ON/OFF
ON/OFF
READ OUT
TTLOUT
TTLOUT
SDATA
SEROUT
Fig. 6-2-1
The VCO, phase comparator, loop filter and frequency
dividing circuit are built in the IC, so the IC can generate
the clock signal by itself.
1 - 4 CLK
COARSE
LATCH
DELAY
2 bits
LOGIC
VCO
MUX
DIV
1 bit
2 bits
SYNTHESIZER
POWER SAVE
TTLIN
1 bit
DIVOUT
TLOAD
6-3
1 bit
ON/OFF
TTLOUT
POLARITY
PECLOUT
1 bit
1 bit
ON/OFF
TTLOUT
1 bit
ON/OFF
TTLOUT
PECLOUT
1 bit
ON/OFF
TTLOUT
1 bit
ON/OFF
REST
TTLOUT
1/2
PECLOUT
1 bit
ON/OFF
UNLOCK
DETECT
WHOLE CHIP
POWER WAVE
PECL
CS
DSYNC
(TTL)
DSYNC
(PECL)
CLK
(TTL)
NCLK
(TTL)
CLK
(PECL)
CLK/2
(TTL)
NCLK/2
(TTL)
CLK/2
(PECL)
UNLOCK
VBB