Cypress S6J3200 Series Manuallines - Страница 3

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If the PCB has only two layers, or requires both logic and balanced microstrip traces on the same layer, the methods

Figure 2

are often more appropriate.

▪

Type-I: Use a GND trace between any logic trace and the nearest trace of any balanced transmission line to act

as a shield.

▪

Type-II: Use at least four times the space between the traces of a balanced microstrip transmission line as the

space between any logic trace and either trace of that balanced transmission line (see Equation 1).

Figure 2

shows examples of Type-I and Type-II recommended layouts.

3.2

Balanced Transmission Lines Spacing

When two or more balanced transmission lines are present in the same layer, do the following:

▪

Type-I: Use a ground (GND) trace between each balanced transmission line to act as a shield.

▪

Type-II: Use twice the space between the traces of a balanced microstrip transmission line and other balanced

transmission lines (see Equation 2).

Figure 3

shows two examples of balanced transmission lines spacing.

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FPD-Link PCB Guidelines for the Traveo Family S6J3200 Series MCUs

Figure 1. Layout Guidelines for 4-layer PCBs

PCB

= 4×

Figure 2. Recommended Layouts

PCB

= 2×

Document No. 002-11139 Rev. *A

Equation 1

Equation 2