Cypress Semiconductor CY7C0251AV Технический паспорт - Страница 5

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Pin Definitions

Left Port

Right Port

R/W

–A

13L

–IO

17L

SEM

INT

BUSY

M/S

GND

Architecture

The

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV consist of an array of 4K, 8K, and

16K words of 16 and 18 bits each of dual-port RAM cells, IO and

address lines, and control signals (CE, OE, RW). These control pins

permit independent access for reads or writes to any location in

memory. To handle simultaneous writes and reads to the same

location, a BUSY pin is provided on each port. Two Interrupt (INT)

pins can be used for port to port communication. Two Semaphore

(SEM) control pins are used for allocating shared resources. With

the M/S pin, the devices can function as a master (BUSY pins are

outputs) or as a slave (BUSY pins are inputs). They also have an

automatic power down feature controlled by CE. Each port has its

own output enable control (OE), which enables data to be read from

the device.

Functional Description

The

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV are low power CMOS 4K, 8K, and

16K ×16/18 dual port static RAMs. Various arbitration schemes are

included on the devices to handle situations when multiple

processors access the same piece of data. There are two ports

permitting independent, asynchronous access for reads and writes

to any location in memory. The devices can be used as standalone

16 or18-bit dual port static RAMs or multiple devices can be

combined to function as a 32 or 36-bit or wider master and slave

dual port static RAM. An M/S pin is provided for implementing 32 or

36-bit or wider memory applications. It does not need separate

master and slave devices or additional discrete logic. Application

areas include interprocessor/multiprocessor designs, communica-

tions status buffering, and dual port video and graphics memory.

Each port has independent control pins: Chip Enable (CE), Read

or Write Enable (R/W), and Output Enable (OE). Two flags are

provided on each port (BUSY and INT). BUSY signals that the

port is trying to access the same location currently being

Document #: 38-06052 Rev. *J

Chip Enable

Read and Write Enable

Output Enable

Address (A

13R

–IO

Data Bus Input and Output

17R

Semaphore Enable

Upper Byte Select (IO

Lower Byte Select (IO

Interrupt Flag

Busy Flag

Master or Slave Select

Power

Ground

No Connect

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Description

–A

for 4K devices; A

–A

–IO

for x16 devices; IO

–IO

for x16 devices; IO

accessed by the other port. The Interrupt flag (INT) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from one

and

port to the other to indicate that a shared resource is in use. The

semaphore logic has eight shared latches. Only one side can

control the latch (semaphore) at any time. Control of a

semaphore indicates that a shared resource is in use. An

automatic power down feature is controlled independently on

each port by a Chip Select (CE) pin.

The

CY7C024AV/024BV/025AV/026AV

CY7C0241AV0251AV/036AV are available in 100-pin Pb-free Thin

Quad Flat Pack (TQFP) and 100-pin TQFP.

Write Operation

Data must be set up for a duration of t

of RW to guarantee a valid write. A write operation is controlled

by either the RW pin (see

Figure 9

on page 12). Required inputs for non-contention opera-

tions are summarized in

and

If a location is being written to by one port and the opposite port

tries to read that location, there must be a port to port flowthrough

delay before the data is read on the output; otherwise the data

read is not deterministic. Data is valid on the port t

data is presented on the other port.

Read Operation

When reading the device, the user must assert both the OE and

CE pins. Data is available t

asserted. If the user wants to access a semaphore flag, then the

SEM pin and OE must be asserted.

Interrupts

The upper two memory locations are for message passing. The

highest

memory

CY7C024AV/024BV/41AV/1FFF for the CY7C025AV/51AV,

for 8K devices; A

–A

for 16K)

–IO

for x18 devices)

–IO

for x18 devices)

before the rising edge

Figure 8

on page 12) or the CE pin (see

Table 1

on page 7.

DDD

after CE or t

ACE

DOE

location

(FFF

Page 5 of 19

and

after the

after OE is

for

the

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