Cypress Semiconductor CY7C1302DV25 Технический паспорт - Страница 9

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TAP Controller Block Diagram
Selection
TDI
Circuitry
TCK
TMS
TAP Electrical Characteristics
Parameter
V
Output HIGH Voltage
OH1
V
Output HIGH Voltage
OH2
V
Output LOW Voltage
OL1
V
Output LOW Voltage
OL2
V
Input HIGH Voltage
IH
V
Input LOW Voltage
IL
I
Input and Output Load Current
X
TAP AC Switching Characteristics
Parameter
t
TCK Clock Cycle Time
TCYC
t
TCK Clock Frequency
TF
t
TCK Clock HIGH
TH
t
TCK Clock LOW
TL
Set-up Times
t
TMS Set-up to TCK Clock Rise
TMSS
t
TDI Set-up to TCK Clock Rise
TDIS
t
Capture Set-up to TCK Rise
CS
Hold Times
t
TMS Hold after TCK Clock Rise
TMSH
t
TDI Hold after Clock Rise
TDIH
t
Capture Hold after Clock Rise
CH
Notes:
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
11. T
and T
refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
12. Test conditions are specified using the load in TAP AC test conditions. Tr/Tf = 1 ns.
Document #: 38-05625 Rev. *A
Instruction Register
29
31
30
Identification Register
.
106
.
Boundary Scan Register
TAP Controller
Over the Operating Range
Description
I
OH
I
OH
I
OL
I
OL
GND ≤ V
Over the Operating Range
Description
0
Bypass Register
2
1
0
.
.
2
1
0
.
.
2
1
0
[10, 13, 15]
Test Conditions
= −2.0 mA
= −100 µA
= 2.0 mA
= 100 µA
≤ V
I
DDQ
[11, 12]
CY7C1302DV25
Selection
TDO
Circuitry
Min.
Max.
1.7
2.1
0.7
0.2
1.7
V
+ 0.3
DD
–0.3
0.7
–5
5
Min.
Max.
Unit
50
20
MHz
20
20
10
10
10
10
10
10
Page 9 of 18
Unit
V
V
V
V
V
V
µA
ns
ns
ns
ns
ns
ns
ns
ns
ns
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