Cypress Semiconductor CY7C131 Технический паспорт - Страница 9

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Cypress Semiconductor CY7C131 Технический паспорт

Switching Waveforms

ADDRESS
DATA OUT
PREVIOUS DATA VALID
CE
OE
DATA OUT
t
PU
I
CC
I
SB
ADDRESS
R
R/W
R
D
INR
ADDRESS
L
BUSY
L
DOUT
L
Notes
20. R/W is HIGH for read cycle.
21. Device is continuously selected, CE = V
22. Address valid prior to or coincident with CE transition LOW.
Document #: 38-06002 Rev. *E
Figure 5. Read Cycle No. 1
Either Port Address Access
t
AA
t
OHA
Figure 6. Read Cycle No. 2
Either Port CE/OE Access
t
ACE
t
DOE
t
LZOE
t
LZCE
Figure 7. Read Cycle No. 3
Read with BUSY, Master: CY7C130 and CY7C131
ADDRESS MATCH
t
PS
t
BLA
and OE = V
.
IL
IL
[20, 21]
t
RC
DATA VALID
[20, 22]
t
HZOE
DATA VALID
[21]
t
RC
t
PWE
VALID
ADDRESS MATCH
t
DDD
t
WDD
CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
t
HZCE
t
PD
t
HD
t
BHA
t
BDD
VALID
Page 9 of 19
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