Cypress Semiconductor CY7C1329H Технический паспорт - Страница 6

Просмотреть онлайн или скачать pdf Технический паспорт для Компьютерное оборудование Cypress Semiconductor CY7C1329H. Cypress Semiconductor CY7C1329H 17 страниц. 2-mbit (64k x 32) pipelined sync sram

Печатать страницу
[2, 3, 4, 5, 6, 7]

Truth Table

Next Cycle
Add. Used
Unselected
None
Unselected
None
Unselected
None
Unselected
None
Unselected
None
Begin Read
External
Begin Read
External
Continue Read
Next
Continue Read
Next
Continue Read
Next
Continue Read
Next
Suspend Read
Current
Suspend Read
Current
Suspend Read
Current
Suspend Read
Current
Begin Write
Current
Begin Write
Current
Begin Write
External
Continue Write
Next
Continue Write
Next
Suspend Write
Current
Suspend Write
Current
ZZ "Sleep"
None
Truth Table for Read/Write
Function
Read
Read
Write Byte A – DQ
A
Write Byte B – DQ
B
Write Bytes B, A
Write Byte C – DQ
C
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – DQ
D
Notes:
2. X = "Don't Care." H =Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW
(BW
,BW
,BW
,BW
), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE
, CE
, and CE
are available only in the TQFP package.
1
2
3
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a
don't care for the remainder of the Write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05673 Rev. *B
Add. Used
CE
CE
1
None
H
X
None
L
L
None
L
X
None
L
L
None
L
X
None
X
X
External
L
H
External
L
H
External
L
H
External
L
H
External
L
H
Next
X
X
Next
X
X
Next
H
X
Next
H
X
Next
X
X
Next
H
X
Current
X
X
Current
X
X
Current
H
X
Current
H
X
Current
X
X
[2, 3]
GW
H
H
H
H
H
H
H
H
H
H
,BW
,BW
A
B
C
CE
ZZ
ADSP
ADSC
2
3
X
L
X
X
L
L
H
L
L
X
L
H
H
L
H
X
H
X
L
L
L
L
L
L
L
L
H
L
L
H
L
L
H
X
L
H
X
L
H
X
L
X
X
L
X
X
L
H
X
L
X
X
L
H
X
L
H
X
L
X
X
L
X
X
L
H
BWE
BW
BW
D
H
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
,BW
) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
D
. Writes may occur only on subsequent clocks
[A:D]
CY7C1329H
ADV
WRITE
OE
L
X
X
X
X
X
X
X
X
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
L
L
X
H
L
X
H
H
L
H
H
L
H
H
L
H
H
L
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BW
BW
C
B
A
X
X
X
H
H
H
H
H
L
H
L
H
H
L
L
L
H
H
L
H
L
L
L
H
L
L
L
H
H
H
Page 6 of 16
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
[+] Feedback