Cypress Semiconductor CY7C1350G Технический паспорт - Страница 3

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Pin Configurations
(continued)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Pin Definitions
Name
I/O
A0, A1, A
Input-
Synchronous
BW
Input-
[A:D]
Synchronous
WE
Input-
Synchronous
ADV/LD
Input-
Synchronous
CLK
Input-Clock
CE
Input-
1
Synchronous
CE
Input-
2
Synchronous
CE
Input-
3
Synchronous
OE
Input-
Asynchronous
CEN
Input-
Synchronous
Document #: 38-05524 Rev. *F
119-Ball BGA Pinout
1
2
3
V
A
A
DDQ
NC/576M
CE
A
2
NC/1G
A
A
DQ
DQP
V
C
C
SS
DQ
DQ
V
C
C
SS
V
DQ
V
DDQ
C
SS
DQ
DQ
BW
C
C
C
DQ
DQ
V
C
C
SS
V
V
V
DDQ
DD
SS
DQ
DQ
V
D
D
SS
DQ
DQ
BW
D
D
D
V
DQ
V
DDQ
D
SS
DQ
DQ
V
D
D
SS
DQ
DQP
V
D
D
SS
NC/144M
A
MODE
NC
NC/72M
A
V
NC
NC
DDQ
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK. A
are fed to the two-bit burst counter.
[1:0]
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD should be
driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE
to select/deselect the device.
2
3
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE
to select/deselect the device.
1
3
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE
to select/deselect the device.
1
2
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
4
5
6
NC/18M
A
A
A
ADV/LD
CE
3
V
A
A
DD
NC
V
DQP
SS
B
V
DQ
CE
SS
B
1
V
DQ
OE
SS
B
NC/9M
BW
DQ
B
B
V
DQ
WE
SS
B
V
V
V
DD
SS
DD
CLK
V
DQ
SS
A
NC
DQ
BW
A
A
V
DQ
CEN
SS
A
A1
V
DQ
SS
A
A0
V
DQP
SS
A
V
NC
A
DD
A
A
NC/36M
NC
NC
NC
Description
CY7C1350G
7
V
DDQ
NC
NC
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC/288M
ZZ
V
DDQ
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