Cypress Semiconductor CY7C1364C Технический паспорт - Страница 4

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Pin Definitions

Name
TQFP
A
, A
, A
37, 36, 32, 33, 34, 35, 43,
0
1
44, 45, 46, 47, 48, 49, 50,
81, 82, 99, 100
BW
, BW
93, 94, 95, 96
A
B
BW
, BW
C
D
GW
BWE
CLK
CE
1
CE
2
CE
3
(for 3 Chip Enable Version)
OE
ADV
ADSP
ADSC
ZZ
DQs
52, 53, 56, 57, 58, 59, 62,
63, 68, 69, 72, 73, 74, 75,
78, 79, 2, 3, 6, 7, 8, 9, 12,
13, 18, 19, 22, 23, 24, 25,
28, 29
V
15, 41, 65, 91
DD
V
17, 40, 67, 90
SS
Document #: 38-05689 Rev. *E
I/O
Input-
Synchronous
Input-
Synchronous
88
Input-
Synchronous
87
Input-
Synchronous
89
Input-
Clock
98
Input-
Synchronous
97
Input-
Synchronous
92
Input-
Synchronous
86
Input-
Asynchronous
83
Input-
Synchronous
84
Input-
Synchronous
85
Input-
Synchronous
64
Input-
Asynchronous
I/O-
Synchronous
Power Supply Power supply inputs to the core of the device.
Ground
Description
Address Inputs used to select one of the 256K address locations.
Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW,
and CE
, CE
, and CE
are sampled active. A
1
2
3
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct
byte writes to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the
rising edge of CLK, a global Write is conducted (ALL bytes are written,
regardless of the values on BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of
CLK. This signal must be asserted LOW to conduct a Byte Write.
Clock Input. Used to capture all synchronous inputs to the device. Also
used to increment the burst counter when ADV is asserted LOW, during
a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.
Used in conjunction with CE
2
ADSP is ignored if CE
is HIGH. CE
1
external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.
Used in conjunction with CE
1
CE
is sampled only when a new external address is loaded.
2
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.
Used in conjunction with CE
1
device.CE
is assumed active throughout this document for BGA. CE
3
is sampled only when a new external address is loaded.
Output Enable, asynchronous input, active LOW. Controls the
direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a Read cycle when emerging
from a deselected state.
Advance Input signal, sampled on the rising edge of CLK, active
LOW. When asserted, it automatically increments the address in a burst
cycle.
Address Strobe from Processor, sampled on the rising edge of
CLK, active LOW. When asserted LOW, A is captured in the address
registers. A
are also loaded into the burst counter. When ADSP and
[1:0]
ADSC are both asserted, only ADSP is recognized. ASDP is ignored
when CE
is deasserted HIGH.
1
Address Strobe from Controller, sampled on the rising edge of
CLK, active LOW. When asserted LOW, A is captured in the address
registers. A
are also loaded into the burst counter. When ADSP and
[1:0]
ADSC are both asserted, only ADSP is recognized.
ZZ "sleep" Input, active HIGH. This input, when High places the
device in a non-time-critical "sleep" condition with data integrity
preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, they
deliver the data contained in the memory location specified by "A"
during the previous clock rise of the Read cycle. The direction of the
pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQ are placed in a tri-state condition.
Ground for the core of the device.
CY7C1364C
feed the 2-bit counter.
[1:0]
and BWE).
[A:D]
and CE
to select/deselect the device.
3
is sampled only when a new
1
and CE
to select/deselect the device.
3
and CE
to select/deselect the
2
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