Cypress Semiconductor CY7C293A Технический паспорт

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Cypress Semiconductor CY7C293A Технический паспорт
92A
Features
Windowed for reprogrammability
CMOS for optimum speed/power
High speed
— 20 ns (commercial)
— 25 ns (military)
Low power
— 660 mW (commercial and military)
Low standby power
— 220 mW (commercial and military)
EPROM technology 100% programmable
Slim 300-mil or standard 600-mil packaging available
5V 10% V
, commercial and military
CC
TTL-compatible I/O
Direct replacement for bipolar PROMs
Capable of withstanding >2001V static discharge

Functional Description

The CY7C291A, CY7C292A, and CY7C293A are high-perfor-
mance 2K-word by 8-bit CMOS PROMs. They are functionally
Logic Block Diagram
A
0
A
1
A
2
ROW
ADDRESS
A
3
A
4
A
5
ADDRESS
A
6
DECODER
A
7
A
8
COLUMN
A
9
ADDRESS
A
10
CS
1
CS
2
CS
3
Cypress Semiconductor Corporation
PROGRAM-
MULTI-
MABLE
PLEXER
ARRAY
POWER
DOWN
7C293A
•
3901 North First Street
CY7C292A/CY7C293A
2K x 8 Reprogrammable PROM
identical, but are packaged in 300-mil (7C291A, 7C293A) and
600-mil wide plastic and hermetic DIP packages (7C292A).
The CY7C293A has an automatic power down feature which
reduces the power consumption by over 70% when deselect-
ed. The 300-mil ceramic package may be equipped with an
erasure window; when exposed to UV light the PROM is
erased and can then be reprogrammed. The memory cells uti-
lize proven EPROM floating-gate technology and byte-wide in-
telligent programming algorithms.
The CY7C291A, CY7C292A, and CY7C293A are plug-in re-
placements for bipolar devices and offer the advantages of
lower power, reprogrammability, superior performance and
programming yield. The EPROM cell requires only 12.5V for
the supervoltage and low current requirements allow for gang
programming. The EPROM cells allow for each memory loca-
tion to be tested 100%, as each location is written into, erased,
and repeatedly exercised prior to encapsulation. Each PROM
is also tested for AC performance to guarantee that after cus-
tomer programming the product will meet DC and AC specifi-
cation limits.
A read is accomplished by placing an active LOW signal on
CS
, and active HIGH signals on CS
1
of the memory location addressed by the address line (A
A
) will become available on the output lines (O
10

Pin Configurations

DIP
O
7
Top View
O
6
A
1
24
7
A
2
23
6
3
22
A
7C291A
O
5
5
4
7C292A
A
21
4
7C293A
A
5
20
3
O
4
6
A
19
2
A
7
18
1
A
8
17
O
0
3
O
9
16
0
10
O
15
1
O
2
11
14
O
2
12
13
GND
O
1
C291A-2
O
0
C291A-1
•
San Jose
•
CY7C291A
and CS
. The contents
2
3
O
).
0
7
LCC/PLCC (Opaque Only)
Top View
V
CC
A
8
A
9
4
3 2 1
28
27
26
A
10
A
25
A
5
4
CS
CS
24
1
A
6
7C291A
3
CS
CS
A
23
7
2
2
CS
A
22
8
1
CS
3
A
21
NC
9
0
O
7C293A
7
NC
20
O
10
O
O
19
O
11
6
0
1314151617
18
12
O
5
O
4
O
3
C291A-3
Window available on
7C291A and 7C293A
only.
CA 95134
•
408-943-2600
March 1986 – Revised May 1993
0
10
1
2
3
7
6