Cypress Semiconductor NoBL CY7C1352G Технический паспорт - Страница 9
Просмотреть онлайн или скачать pdf Технический паспорт для Компьютерное оборудование Cypress Semiconductor NoBL CY7C1352G. Cypress Semiconductor NoBL CY7C1352G 13 страниц. 4-mbit (256k x 18) pipelined sram with nobl architecture
Печатать страницуSwitching Waveforms
[18, 19, 20]
Read/Write Timing
1
CLK
t
t
CENS
CENH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
[A:B]
A1
ADDRESS
t
t
AS
AH
Data
In-Out (DQ)
OE
WRITE
D(A1)
Notes:
18. For this waveform ZZ is tied low.
19. When CE is LOW: CE
is LOW, CE
1
20. Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional.
Document #: 38-05514 Rev. *D
2
3
4
t CYC
t
t
CL
CH
A2
A3
t
t
DS
DH
D(A1)
D(A2)
WRITE
BURST
READ
D(A2)
WRITE
Q(A3)
D(A2+1)
DON'T CARE
is HIGH and CE
is LOW. When CE is HIGH: CE
2
3
5
6
7
A4
A5
t
CO
t
t
DOH
CLZ
D(A2+1)
Q(A3)
Q(A4)
t
OEHZ
READ
BURST
WRITE
Q(A4)
READ
D(A5)
Q(A4+1)
UNDEFINED
is HIGH or CE
is LOW or CE
1
2
CY7C1352G
8
9
10
A6
A7
t
t
OEV
CHZ
Q(A4+1)
D(A5)
Q(A6)
t
DOH
t
OELZ
READ
WRITE
DESELECT
Q(A6)
D(A7)
is HIGH.
3
Page 9 of 12
[+] Feedback