Cypress Semiconductor Perform STK14D88 Руководство - Страница 5

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SRAM READ Cycles #1 and #2
Symbols
NO.
#1
#2
1
t
t
ELQV
ACS
[4]
[4]
2
t
t
t
AVAV
ELEH
RC
[5]
[5]
3
t
t
t
AVQV
AVQV
AA
4
t
t
GLQV
OE
[5]
[5]
5
t
t
t
AXQX
AXQX
OH
6
t
t
ELQX
LZ
[6]
7
t
t
EHQZ
HZ
8
t
t
GLQX
OLZ
[6]
9
t
t
GHQZ
OHZ
[3]
10
t
t
ELICCH
PA
[3]
11
t
t
EHICCL
PS
ADDRESS
DQ (DATA OUT)
Notes
4. W must be high during SRAM READ cycles.
5. Device is continuously selected with E and G both low.
6. Measured ± 200mV from steady state output voltage.
7. HSB must remain high during READ and WRITE cycles.
Document Number: 001-52037 Rev. **
Parameter
Alt.
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to
Output Active
Address Change or Chip Disable to
Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Figure 4. SRAM READ Cycle 1: Address Controlled
5
t
AXQX
Figure 5. SRAM READ Cycle 2: E Controlled
1
6
3
4
8
10
STK14D88-25 STK14D88-35 STK14D88-45
Min
Max
25
25
25
12
3
3
10
0
10
0
25
2
t
AVAV
3
t
AVQV
DATA VALID
[4, 7]
2
29
STK14D88
Min
Max
Min
Max
35
45
35
45
35
45
15
20
3
3
3
3
13
15
0
0
13
15
0
0
35
45
[4, 5, 6]
11
7
9
Page 5 of 17
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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