Cypress Semiconductor STK22C48 Технический паспорт - Страница 3
Просмотреть онлайн или скачать pdf Технический паспорт для Компьютерное оборудование Cypress Semiconductor STK22C48. Cypress Semiconductor STK22C48 15 страниц. 16 kbit (2k x 8) autostore nvsram
Печатать страницуDevice Operation
The STK22C48 nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK22C48 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The STK22C48 performs a Read cycle whenever CE and OE are
LOW while WE and HSB are HIGH. The address specified on
pins A
determines the 2,048 data bytes accessed. When the
0–10
Read is initiated by an address transition, the outputs are valid
after a delay of t
(Read cycle 1). If the Read is initiated by CE
AA
or OE, the outputs are valid at t
(Read cycle 2). The data outputs repeatedly respond to address
changes within the t
access time without the need for transi-
AA
tions on any control input pins, and remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the Write cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
are written into the memory if it has valid t
0–7
the end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common IO lines. If OE is left LOW,
internal circuitry turns off the output buffers t
LOW.
AutoStore Operation
During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
pin drops below V
CC
automatically disconnects the V
operation is initiated with power provided by the V
Figure 2
shows the proper connection of the storage capacitor
(V
) for automatic store operation. A charge storage capacitor
CAP
between 68 µF and 220 µF (+20%) rated at 6V should be
Document Number: 001-51000 Rev. **
or at t
, whichever is later
ACE
DOE
, before
SD
after WE goes
HZWE
CC
pin. This stored
CAP
, the part
SWITCH
pin from V
. A STORE
CAP
CC
capacitor.
CAP
Figure 2. AutoStore Mode
In system power mode, both V
+5V power supply without the 68 μF capacitor. In this mode, the
AutoStore function of the STK22C48 operates on the stored
system charge as power goes down. The user must, however,
guarantee that V
does not drop below 3.6V during the 10 ms
CC
STORE cycle.
To prevent unneeded STORE operations, automatic STOREs
and those initiated by externally driving HSB LOW are ignored,
unless at least one
WRITE
recent STORE or RECALL cycle. An optional pull up resistor is
shown connected to HSB. This is used to signal the system that
the AutoStore cycle is in progress.
AutoStore Inhibit mode
If an automatic STORE on power loss is not required, then V
is tied to ground and +5V is applied to V
the AutoStore Inhibit mode, where the AutoStore function is
to
disabled. If the STK22C48 is operated in this configuration, refer-
ences to V
are changed to V
CC
In this mode, STORE operations are triggered with the HSB pin.
It is not permissible to change between these three options "on
the fly".
STK22C48
and V
are connected to the
CC
CAP
operation takes place since the most
(Figure
3). This is
CAP
throughout this data sheet.
CAP
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