Fujitsu D2860 Teknik Kılavuz - Sayfa 13

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Features

3.1

Processors

– 1 or 2 Intel

Xeon™ processors of the 5500 series

– 2 processor sockets LGA1366 for Intel

– integrated memory controller (DDR3)

– 32 KB L1 cache (on-die data cache per core)

– 32 KB L1 cache (on-die instruction cache per core)

– 256 KB L2 cache (mid-level per core)

– up to 8 MB on chip shared L3 cache (among all cores)

– 2x Intel® QuickPath Interconnect with up to 6,4 GT/s in each direction

Main memory

– 9 slots for main memory DDR3 800 / 1066 / 1333 single-, dual- or quad-

ranked DIMM memory modules with 2 GB, 4 GB and 8 GB

– buffered and unbuffered DIMMs with ECC are supported, no mixed

equipping allowed

– maximum 72 GB of memory

– minimum 2 GB (1 memory module)

– maximum 32 Gbit/s band width (DDR3)

– CPU0 has 2 DIMM slots for memory rows per channel, CPU1 has 1 DIMM

slot for memory row per channel

– ECC multiple-bit error detection and single-bit error correction

– memory scrubbing functionality

– Single Device Data Correction (SDDC) function (Chipkill™)

– Mirroring

– Sparing

– Locking

Chips on the system board

– Intel

5500 chipset

– Intel

ICH10 Base

– 2x Intel

dual-channel Gigabit Ethernet controller Intel

– Hard disk controller LSI1064E SAS for 2 SAS hard disks

– TPM 1.2 Infineon SLB9635 TT1.2 card (option)

– Board Management controller iRMC S2 with integrated graphic controller

D2860 (BX920)

Xeon™ processors

Technical Manual

82575X2