Chrontel CH7515A Yerleşim Tasarım Kılavuzu - Sayfa 9

Yarı İletkenler Chrontel CH7515A için çevrimiçi göz atın veya pdf Yerleşim Tasarım Kılavuzu indirin. Chrontel CH7515A 15 sayfaları.

Sayfayı Yazdır
CHRONTEL
RB
CH7515A I2C
Master Activity
CH7515A
PSEL [2:0]
RB
CH7515A I2C
Master Activity
CH7515A
PSEL [2:0]
Figure 10: Typical cases to control CH7515A PSEL [2:0] by host chip
Note:
1. The PSEL pins must keep stable values in 150ms after the RB signal is given to CH7515A RB pin. Otherwise,
a reset signal must be given again.
2. All the case2 must be finished before VBIOS works. Otherwise, some BIOS pictures will be lost.
• PWM_OUT
The output Frequency from PWM_OUT can be up to 400 KHz. Its duty cycle rang is from 0% to 100%. Or this signal
can use PWM bypass mode way to output PWM signal. The voltage level is 3.3V. The detail information can be
reference to datasheet.
• PWM_IN
PWM_IN has two work modes: Bypass mode and Duty Cycle Multiplication with AUX CH mode.
In bypass mode, the input frequency to PWM_IN can be up to 1MHz.In Duty Cycle Multiplication with AUX CH
mode, the input frequency to PWM_IN can be up to 50 KHz. Despite in which mode, the voltage level is 3.3V.
• Reserved
Reserved pin (pin 2) should be left open in the application.
2.9
Important Design Considerations
206-1000-021
Rev 1.0
IDLE
Loading Firmware
Random Values
Case 1: CH7515A PSEL [2:0] settles before it starts loading LVDS configurations
Loading LVDS
IDLE
Loading Firmware
Configurations
Wrong LVDS
configurations!
Random Values
Case 2: CH7515A PSEL [2:0] cannot settle before it starts loading LVDS configurations
U1
103
PWM_IN
102
PWM_OUT
CH7515A
Figure 11: PWM Control connections
2020-07-15
Loading LVDS
IDLE
Configurations
Correct LVDS Panel Selection Value
RB pulse generated by
Customers host chip
IDLE
Loading Firmware
Correct LVDS Panel Selection Value
PWM_IN
PWM_OUT
AN-B021
Loading LVDS
Configurations
Correct LVDS
configurations!
9