Alpha Data ADM-VPX3-9Z5-RTM Kullanıcı Kılavuzu - Sayfa 12
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Sayfayı Yazdır3.6 HS MIO Interfaces
The ADM-VPX3-9Z5-RTM allows support for the following PS GTR interfaces: displayport, ethernet and SATA.
In order for the interfaces to be routed out correctly The PS GTR serial interfaces should be configured as
highlighted in the table below:
3.7 Ethernet Phy Interface Signals
The reset_n pin of the Ethernet Phy is connected directly to the VPX system reset.
The Ethernet Phy MDIO BUS interface should be configured as shown in the table below:
3.8 Display Port AUX signals
The Display Port AUX interface should be configured as shown in the table below:
Page 8
Figure 5 : HS-MIO Configuration
Signal Name
MDC
MDIO
Table 4 : MDIO pins
Signal Name
DP_AUX_OUT
DP_HPD
DP_OE
DP_AUX_IN
Table 5 : DPAUX pins
ADM-VPX3-9Z5-RTM User Manual
FPGA Pin
PSMIO76 (AH31)
PSMIO77 (AG31)
FPGA Pin
PSMIO34 (P27)
PSMIO35 (N29)
PSMIO36 (T27)
PSMIO37 (N30)
V1.1 - 18th August 2022
Functional Description
ad-ug-1392_v1_1.pdf