Cisco UCS C480 M5 Manuel - Sayfa 4

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Memory Organization

The standard memory features are:

—

Memory is organized with six memory channels per CPU, with up to two memory devices per

channel, as shown in

upper bay. CPU1 and CPU2 control up to 24 DIMMs and CPU3 and CPU4 also control up to 24

DIMMs, for a total of up to 48 DIMMs total for the server.

Figure 2

C480 Memory Organization

Chan A

Chan B

Chan C

CPU1/

CPU3

Chan D

Chan E

Chan F

24 DIMMS

6 memory channels per CPU,

up to 2 DIMMs per channel

Clock speed: 2666 MHz or 2933 MHz depending on CPU type

Ranks per DIMM: 1, 2, 4, or 8

DIMM operational voltage: 1.2 V

Registered ECC DDR4 DIMMS (RDIMMs), Load-reduced DIMMs (LRDIMMs),

through-silicon via DIMMs (TSV DIMMs), or Intel

Modules (DCPMMs).

Figure

2. CPU1 and CPU2 are in the lower bay; CPU3 and CPU 4 are in the

Chan G

Chan H

Chan J

CPU 2/

CPU4

Chan K

Chan L

Chan M

Optane

H2 H1

Cisco UCS C480 M5 Memory Guide

DC Persistent Memory