Cypress Semiconductor CY62147DV18 Şartname Sayfası - Sayfa 5

Bilgisayar Donanımı Cypress Semiconductor CY62147DV18 için çevrimiçi göz atın veya pdf Şartname Sayfası indirin. Cypress Semiconductor CY62147DV18 12 sayfaları. Mobl2 4-mb (256k x 16) static ram

Sayfayı Yazdır
Data Retention Waveform
wqewqewq
V
CC
CE or
BHE.BLE
Switching Characteristics Over the Operating Range
Parameter
Read Cycle
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE LOW to Data Valid
ACE
t
OE LOW to Data Valid
DOE
t
OE LOW to LOW Z
LZOE
t
OE HIGH to High Z
HZOE
t
CE LOW to Low Z
LZCE
t
CE HIGH to High Z
HZCE
t
CE LOW to Power-Up
PU
t
CE HIGH to Power-Down
PD
t
BLE / BHE LOW to Data Valid
DBE
t
BLE / BHE LOW to Low Z
LZBE
t
BLE / BHE HIGH to HIGH Z
HZBE
[13]
Write Cycle
t
Write Cycle Time
WC
t
CE LOW to Write End
SCE
t
Address Set-up to Write End
AW
t
Address Hold from Write End
HA
t
Address Set-up to Write Start
SA
t
WE Pulse Width
PWE
t
BLE / BHE LOW to Write End
BW
t
Data Set-Up to Write End
SD
t
Data Hold from Write End
HD
t
WE LOW to High-Z
HZWE
t
WE HIGH to Low-Z
LZWE
Notes:
9.
BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signal or by disabling both BHE and BLE.
10. Test conditions for all parameters other than three-state parameters assume signal transition time of 1V/ns or less, timing reference levels of V
pulse levels of 0 to V
, and output loading of the specified I
CC(typ.)
11. At any given temperature and voltage condition, t
given device.
12. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedence state.
HZOE
HZCE
HZBE
HZWE
13. The internal Write time of the memory is defined by the overlap of WE, CE = V
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05343 Rev. *B
[9]
DATA RETENTION MODE
V
CC(min)
t
CDR
Description
[11]
[11, 12]
[11]
[11, 12]
[11]
[11, 12]
[11, 12]
[11]
/I
as shown in the "AC Test Loads and Waveforms" section.
OL
OH
is less than t
, t
HZCE
LZCE
HZBE
V
> 1.0 V
DR
[10.]
55 ns
Min.
Max.
Min.
55
70
55
10
10
55
25
5
16
10
10
20
0
55
55
10
10
20
55
70
40
50
40
50
0
0
40
45
40
50
25
30
0
20
10
10
is less than t
, t
is less than t
LZBE
HZOE
LZOE
, BHE and/or BLE = V
. All signals must be ACTIVE to initiate a write and any
IL
IL
CY62147DV18
MoBL2™
V
CC(min)
t
R
70 ns
Max.
Unit
ns
70
ns
ns
70
ns
35
ns
5
ns
16
ns
ns
25
ns
0
ns
70
ns
70
ns
ns
25
ns
ns
ns
ns
0
ns
0
ns
ns
ns
ns
0
ns
25
ns
ns
/2, input
CC(typ)
, and t
is less than t
for any
HZWE
LZWE
Page 5 of 11
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