Cypress Semiconductor CY7C0241AV Şartname Sayfası - Sayfa 13

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Switching Waveforms
A
–A
0
2
SEM
IO
0
t
SA
R/W
OE
Figure 11. Timing Diagram of Semaphore Contention
A
–A
0L
2L
R/W
L
SEM
L
A
–A
0R
2R
R/W
R
SEM
R
Notes
43. CE = HIGH for the duration of the above timing (both write and read cycle).
44. IO
= IO
= LOW (request semaphore); CE
0R
0L
45. Semaphores are reset (available to both ports) at cycle start.
46. If t
is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
SPS
Document #: 38-06052 Rev. *J
(continued)
Figure 10. Semaphore Read After Write Timing, Either Side
VALID ADRESS
t
AW
t
HA
t
SCE
t
SD
DATA
VALID
IN
t
HD
t
PWE
WRITE CYCLE
MATCH
t
SPS
MATCH
= CE
= HIGH.
R
L
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
t
SAA
VALID ADRESS
t
ACE
t
SOP
t
t
SWRD
DOE
t
SOP
READ CYCLE
[44, 45, 46]
[43]
t
OHA
DATA
VALID
OUT
Page 13 of 19
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