Cypress Semiconductor CY7C1018CV33 Şartname Sayfası - Sayfa 4
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Switching Waveforms
[11, 12]
Read Cycle No. 1
ADDRESS
DATA OUT
PREVIOUS DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
HIGH IMPEDANCE
DATA OUT
t
V
PU
CC
SUPPLY
CURRENT
Write Cycle No. 1 (CE Controlled)
ADDRESS
CE
WE
DATA I/O
Notes:
11. Device is continuously selected. OE, CE = V
12. WE is HIGH for Read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = V
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05131 Rev. *D
t
AA
t
OHA
[12, 13]
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
50%
[14, 15]
t
t
SA
t
AW
.
IL
.
IH
t
RC
DATA VALID
WC
t
SCE
t
SCE
t
PWE
t
SD
DATA VALID
CY7C1018CV33
DATA VALID
t
HZOE
t
HZCE
HIGH
IMPEDANCE
t
PD
50%
t
HA
t
HD
Page 4 of 7
ICC
ISB
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