Cypress Semiconductor CY7C1231H Şartname Sayfası - Sayfa 10

Bilgisayar Donanımı Cypress Semiconductor CY7C1231H için çevrimiçi göz atın veya pdf Şartname Sayfası indirin. Cypress Semiconductor CY7C1231H 13 sayfaları. Cypress 2-mbit (128k x 18) flow-through sram with nobl architecture specification sheet

Sayfayı Yazdır
Switching Waveforms
NOP, STALL and Deselect Cycles
1
CLK
CEN
CE
ADV/LD
WE
BW
[A:B]
A1
ADDRESS
DQ
COMMAND
WRITE
D(A1)
[22, 23]
ZZ Mode Timing
CLK
ZZ
I
SUPPLY
ALL INPUTS
(except ZZ)
Outputs (Q)
Notes:
21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
22. Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device.
23. I/Os are in tri-state when exiting ZZ sleep mode.
Document #: 001-00207 Rev. *B
(continued)
[18, 19, 21]
2
3
4
A2
A3
D(A1)
Q(A2)
READ
STALL
READ
Q(A2)
Q(A3)
DON'T CARE
t ZZ
t
ZZI
I
DDZZ
5
6
7
A4
Q(A3)
D(A4)
WRITE
STALL
NOP
D(A4)
UNDEFINED
High-Z
DON'T CARE
CY7C1231H
8
9
10
A5
t CHZ
Q(A5)
t DOH
READ
DESELECT
CONTINUE
Q(A5)
DESELECT
t
ZZREC
t RZZI
DESELECT or READ Only
Page 10 of 12
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