Cypress Semiconductor CY7C131 Şartname Sayfası - Sayfa 10
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Switching Waveforms
Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—Either Port
ADDRESS
CE
R/W
DATA
IN
OE
t
HZOE
D
OUT
Figure 9. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
ADDRESS
CE
R/W
DATA
IN
DATA
OUT
Notes
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
and for data to be placed on the bus for the required t
24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document #: 38-06002 Rev. *E
(continued)
Either Port
t
WC
t
SCE
t
AW
t
SA
t
WC
t
SCE
t
AW
t
SA
t
HZWE
.
SD
t
HA
t
PWE
t
t
SD
HD
DATA VALID
HIGH IMPEDANCE
t
HA
t
PWE
t
t
SD
HD
DATA VALID
t
LZWE
HIGH IMPEDANCE
or t
+ t
to allow the data I/O pins to enter high impedance
PWE
HZWE
SD
CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
[16, 23]
[17, 24]
Page 10 of 19
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