Cypress Semiconductor CY7C1336H Şartname Sayfası - Sayfa 5

Bilgisayar Donanımı Cypress Semiconductor CY7C1336H için çevrimiçi göz atın veya pdf Şartname Sayfası indirin. Cypress Semiconductor CY7C1336H 16 sayfaları. Cypress 2-mbit (64k x 32) flow-through sync sram specification sheet

Sayfayı Yazdır
ZZ Mode Electrical Characteristics
Parameter
I
Sleep mode standby current
DDZZ
t
Device operation to ZZ
ZZS
t
ZZ recovery time
ZZREC
t
ZZ Active to sleep current
ZZI
t
ZZ Inactive to exit sleep current
RZZI
[2, 3, 4, 5, 6]

Truth Table

Cycle Description
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Sleep Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
2. X = "Don't Care." H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW
(BW
, BW
, BW
, BW
), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 001-00210 Rev. *A
PRELIMINARY
Description
ADDRESS
Used
CE
CE
CE
1
2
None
H
X
X
None
L
L
X
None
L
X
H
None
L
L
X
None
X
X
X
None
X
X
X
External
L
H
L
External
L
H
L
External
L
H
L
External
L
H
L
External
L
H
L
Next
X
X
X
Next
X
X
X
Next
H
X
X
Next
H
X
X
Next
X
X
X
Next
H
X
X
Current
X
X
X
Current
X
X
X
Current
H
X
X
Current
H
X
X
Current
X
X
X
Current
H
X
X
, BW
, BW
A
B
Test Conditions
ZZ > V
– 0.2V
DD
ZZ > V
– 0.2V
DD
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
ZZ
ADSP
ADSC
ADV WRITE OE CLK
3
L
X
L
X
L
L
X
X
L
L
X
X
L
H
L
X
L
H
L
X
H
X
X
X
L
L
X
X
L
L
X
X
L
H
L
X
L
H
L
X
L
H
L
X
L
H
H
L
L
H
H
L
L
X
H
L
L
X
H
L
L
H
H
L
L
X
H
L
L
H
H
H
L
H
H
H
L
X
H
H
L
X
H
H
L
H
H
H
L
X
H
H
, BW
) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
C
D
[A: D]
CY7C1336H
Min.
Max.
Unit
40
mA
2t
CYC
2t
CYC
2t
CYC
0
DQ
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
X
Tri-State
X
L
L-H
Q
X
H
L-H
Tri-State
L
X
L-H
D
H
L
L-H
Q
H
H
L-H
Tri-State
H
L
L-H
Q
H
H
L-H
Tri-State
H
L
L-H
Q
H
H
L-H
Tri-State
L
X
L-H
D
L
X
L-H
D
H
L
L-H
Q
H
H
L-H
Tri-State
H
L
L-H
Q
H
H
L-H
Tri-State
L
X
L-H
D
L
X
L-H
D
. Writes may occur only on subsequent clocks
Page 5 of 15
ns
ns
ns
ns
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