Cypress Semiconductor CY7C1353G Şartname Sayfası - Sayfa 11
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Sayfayı YazdırSwitching Waveforms
NOP, STALL and DESELECT Cycles
1
CLK
CEN
CE
ADV/LD
WE
BW
[A:B]
A1
ADDRESS
DQ
COMMAND
WRITE
D(A1)
ZZ Mode Timing
[23,24]
CLK
ZZ
I
SUPPLY
ALL INPUTS
(except ZZ)
Outputs (Q)
Notes:
22.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
23.Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
24.DQs are in high-Z when exiting ZZ sleep mode
Document #: 38-05515 Rev. *E
[19, 20, 22]
2
3
4
A2
A3
D(A1)
Q(A2)
READ
STALL
READ
Q(A2)
Q(A3)
DON'T CARE
t ZZ
t
ZZI
I DDZZ
5
6
7
A4
Q(A3)
D(A4)
WRITE
STALL
NOP
D(A4)
UNDEFINED
t RZZI
DESELECT or READ Only
High-Z
DON'T CARE
CY7C1353G
8
9
10
A5
t CHZ
Q(A5)
t DOH
READ
DESELECT
CONTINUE
Q(A5)
DESELECT
t
ZZREC
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