Cypress Semiconductor CY7C138 Şartname Sayfası - Sayfa 12
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Sayfayı YazdırSwitching Waveforms
Left Side Sets INT
:
R
ADDRESS
L
CE
L
R/W
L
INT
R
Right Side Clears INT
R
ADDRESS
R
CE
R
R/W
R
OE
R
INT
R
Right Side Sets INT
:
L
ADDRESS
R
CE
R
R/W
R
INT
L
Left Side Clears INT
:
L
ADDRESS
R
CE
L
R/W
L
OE
L
INT
L
Notes
31. t
depends on which enable pin (CE
HA
32. t
or t
depends on which enable pin (CE
INS
INR
Document #: 38-06037 Rev. *D
(continued)
Figure 14. Interrupt Timing Diagrams
t
WC
WRITE FFF
t
[32]
INS
:
t
[32]
INR
t
WC
WRITE FFE
[32]
t
INS
t
or R/W
) is deasserted first.
L
L
or R/W
) is asserted last.
L
L
t
[31]
HA
READ FFF
t
[31]
HA
READ FFE
[32]
INR
CY7C138, CY7C139
t
RC
t
RC
Page 12 of 17
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