Cypress Semiconductor STK11C68 Şartname Sayfası - Sayfa 2

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Pin Configurations

Pin Definitions

Pin Name
Alt
IO Type
A
–A
Input
0
12
DQ
-DQ
Input or
0
7
Output
Input
WE
W
Input
CE
E
Input
OE
G
V
Ground
SS
V
Power Supply Power Supply Inputs to the Device.
CC
Document Number: 001-50638 Rev. **
Figure 1. Pin Diagram - 28-Pin SOIC/DIP and 28-Pin LLC
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
Bidirectional Data IO Lines. Used as input or output lines depending on operation.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the
IO pins is written to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the Device. The device is connected to ground of the system.
Description
STK11C68
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