EG&G ORTEC 426 Kullanım ve Servis Kılavuzu - Sayfa 11

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signal from the collector of Q11 , Q13 turns off and Q12

conducts the quiescent current through R33, the common-

emitter resistor. The current through Q12 wil l flow unti l

capacitor C8 charges enough to cause the base of Q13 to

equal the base voltage of Q12. At this time Q13 wil l return

to its stable state, conducting the quiescent current through

R33.

The duration that Q12 conducts is controlled by the time

constant of R34 and R35 and C8. The gate width is then

seen to be controlled by the setting of R35. The positive

pulse generated at the collector of Q13 is fed to the current

switch Q4 and Q5 to switch the current flowing in R9

through Q5 during the gating period.

The above circuit description assumes the mode switch to be

in the Normal position. With the switch in Pulse Inhibit

position the base of Q5 is held at ground while the base of

Q4 is held at —0.6 V. Therefore the current switch wi l l have

the current through R9 flowing in Q5, and Q4 will be cut

off. With the current switch in this condition Q2 is saturated

and Q3 is cut off, thereby passing all input signals to the

base of Q6.

With the application of an Enable input pulse a positive

signal is applied to Q4 base through capacitor C2, and the

transistors Q2 and Q3 change state and thereby block

passage of signals from the input to the base of Q6. Conse

quently, there is no output from the linear gate.

In the DC Inhibit position the same conditions apply to the

current switch Q4 and Q5, and the current switch can

change state only with the application of a positive input on

the DC Inhibit Input CN4. Notice that in the DC Inhibit

position the current switch is dc-coupled to the connector

CN4 and therefore absolute control of the Linear Gate is

available on connector CN4.

6. MAIIMTENAIMCE

6.1. TESTING THE PERFORMANCE

OF THE LINEAR GATE

Use the following procedure to check the performance of

the 426:

The following paragraphs are intended as an aid in the

installation and checkout of the ORTEC 426. These

instructions present information on front panel controls,

waveforms at test points and output connectors. It wil l be

helpful to refer to the schematic and block diagram at the

end of this manual.

1 . Feed the 419 Pulse Generator output into the 410 Linear

Amplifier. Feed the Bipolar Output of the 410 into the 407.

Crossover Pickoff. Feed the Output from the 407 into the

Enable input of the 426. Set the 410 pulse shaping mode to

Double RC (DRC), i.e.. Integrator, First Differentiator, and

Second Differentiator to 0.2 jdsec.

The following, or equivalent, test equipment is needed:

ORTEC 419 Pulse Generator

Tektronix Model 580 Series Osci l loscope

1000 BNC Terminators

Vacuum Tube Voltmeter

ORTEC 410 Linear Amplifier

ORTEC 427 Delay Amplifier

ORTEC 407 Crossover Pickoff

The following preliminary procedures should be observed:

1. Visually check module for possible damage due to

shipment.

2. Plug module into Bin and check for proper mechanical

alignment.

3. Connect ac power to ORTEC 401/402 Bin and Power

Supply.

4. Switch ac power on and check the dc power supply

voltages at the test points on the Power Supply control

panel on the 401 .

2. Also feed the Bipolar Output of the 410 into the ORTEC

427 Delay Amplifier. The output of the 427 should be

approximately 0.5 V.

3. Observe the output of the 426. Adjust the trim potenti

ometer at the top of the board for a minimum pedestal.

4. The amplitude of both the initial and final transient

negative spikes should not exceed 300 mV.

5. Feed the Output of the 427 into the l inear Input of the

426. Measure the input and output of the 426. The input

should not differ from the output by more than 80 mV.

6. Adjust the410 gain controlsto give a -t-8-V pulse into the

linear Input of the 426. The Linear Gate Output should be

8 ± 0.4 V. Load the 426 Output with lOOil. The output

pulse amplitude should not decrease more than 0.15 V.

7. Adjust the 410 Linear Amplifier gain controls to give a

-r11 V pulse into the Input of the Linear Gate. The Linear

Gate Output should saturate at greater than 20 V.