4ms Dual Looping Delay Посібник користувача - Сторінка 11

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Audio Bootloader

The DLD contains a bootloader that is used to update the firmware by playing an audio file the In B jack on the right side of

the module. Although using the In A jack may work some times, it's recommended to use the In B jack for more reliable

operation.

Firmware audio files can be downloaded at http://4mscompany.com/dld.php

1. To enter bootloader mode, power off the DLD and connect a computer or smart phone audio output to the In B jack.

Either a stereo or mono cable is fine. Connect the Out B jack to an amp/speakers so you can listen.

Remove your phone case, it may be preventing the cable from fully plugging in.

2. Set the computer/phone's volume to 100% and the audio player software to 100% volume. Turn off all audio and

vibrate notifications (use Airplane mode). Close any applications that make notification sounds such as Facebook.

3. Depress both Reverse buttons (A and B) and the Ping button while powering on the DLD. When you see the Channel

A Hold button blink, the DLD is ready to receive firmware. Release the buttons.

4. Begin playing the file. Immediately you should see red Channel A Loop LED blink. The blue light will flash from time to

time as well. Do not interrupt the process! You can monitor the audio by listening to the Out B jack.

5. If the monitored audio stops before the end of the file and/or the lights stop blinking, an error has occurred and you

should try again. Verify the cable is not loose, all sounds/vibrate/notifications are off, and that you have downloaded

the audio file completely (avoid streaming or playing from the browser). Check the volume is at 100%. Remove the

protection case from your smart phone. Stop the audio file, reset it back to the start, and tap Reverse A button to reset.

The Hold A button should light up. Play the file from the beginning again.

6. If the file loads successfully, the DLD will immediately start running. In some cases, you may need to do a Factory

Reset (see Factory Reset section).

**Estimated late June 2016, the open-source licensed source files (in C, for compiling with gcc-arm) can be found at

https://www.github.com/4ms/DLD

The audio files are not at this location, they are available from http://4mscompany.com/dld.php

Clock Bus Jumper

Clock bus is a 1:1 clock that runs along the Gate pin of the Doepfer-specified power system. Modules such as the 4ms QCD,

RCD, SCM, and PEG are compatible with the clock bus system. The DLD fully buffers the bus clock and has diode protection

and a pull-down resistor. To use the DLD on a clock bus system, install the jumper in one of two positions:

Bus Clock Send:

Connect the jumper on the upper position ("BUS CLK SEND") to send the master

clock from the DLD to the clock bus. The clock will be identical (but separately

buffered) as the signal on the Clock Out jack.

It is not recommended to have more than one device sending (master) on the same

clock bus system. The DLD will not be damaged, but results will be unpredictable.

Receive Clock Bus:

Connect the jumper on the lower position ("BUS CLK RECV") to receive a ping clock

from the clock bus. The signal on the bus clock will be automatically patched to the

Ping jack. By plugging a cable into the Ping jack, the bus clock will be disconnected

from the DLD.

Note: When receiving a bus clock, you must stop the external bus clock or patch a

dummy cable into the Ping jack in order to use the Ping tap button.

This is the factory default for some DLD serial numbers less than 500.

Clock Bus Disabled:

Remove the jumper completely to disable clock bus support. The jumper may be

parked on one pin.