Dialog Semiconductor SLG46824 Посібник з програмування - Сторінка 7

Переглянути онлайн або завантажити pdf Посібник з програмування для Материнська плата Dialog Semiconductor SLG46824. Dialog Semiconductor SLG46824 15 сторінок. In-system

Друкувати сторінку

1. Hardware Requirements

ISPG-SLG46824/6

SLG46824/6

C Signal Specifications

3.1 COMMANDS

3.1.1 Write Command

Write access to the NVM is possible by setting A3 A2 A1 A0 to "0000", which allows serial write data for a single page only. Upon

receipt of the proper Control Byte and Word Address bytes, the SLG46824/6 will send an ACK. The device will then be ready to

receive page data, which is 16 sequential writes of 8-bit data words. The SLG46824/6 will respond with an ACK after each data

word is received. The addressing device, such as a bus Master, must then terminate the write operation with a Stop condition

after all page data is written. At that time the GPAK will enter an internally self-timed write cycle, which will be completed within

= 20 ms (max). While the data is being written into the NVM Memory Array, all inputs, outputs, internal logic and I

to the Register data will be operational/valid.

Start

Bus Activity

Control Byte

bit

SDA LINE

X X X X

Control

Code

Address

3.1.2 Verify Command

The Random Sequential Read command can be used for verification. The command starts with a Control Byte (with R/W bit set

to "0", indicating a write command) and Word Address to set the internal byte address, followed by a Start bit, and then the Control

Byte for the read (exactly the same as the Byte Write command). The Start bit in the middle of the command will halt the decoding

of a Write command, but will set the internal address counter in preparation for the second half of the command. After the Start

bit, the Bus Master issues a second Control Byte with the R/W bit set to "1", after which the SLG46824/6 issues an Acknowledge

bit, followed by the requested eight data bits. Once the SLG46824/6 transmits the first data byte, the Bus Master issues an

Acknowledge bit. The Bus Master can continue reading sequential bytes of data, and will terminate the command with a Stop

condition.

Start

bit

Control Byte

Bus Activity

SDA

X X X X

LINE

Control

Block

Code

Address

Acknowledge

bit

Word Address (n)

ACK

Block

R/W bit

Figure 5: Page Write Command Example

Acknowledge

bit

Word Address (n)

ACK

Read bit

Figure 6: Random Sequential Read Command

Revision 1.1

Data (n)

ACK

edge

Control Byte

S X X X X A

ACK

Control

Block

Code

Address

Read bit

7 of 15

C access

Acknowledge

bit

Data (n+1)

Data (n + 15)

ACK

Stop

Data (n)

Data (n + x)

ACK

No Ack

bit

4-Mar-2019

bit

Stop

bit