Chrontel CH7034B Примітки щодо застосування - Сторінка 6
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After C
(crystal load capacitance) is properly selected, care should be taken to make sure the crystal is not
L
operating in an excessive drive level specified by the crystal manufacturer. Otherwise, the crystal will age quickly
and that in turn will affect the operating frequency of the crystal.
For detail considerations of crystal oscillator design, please refer to AN-06.
2.4
Serial Port Control for CH7034B
• SPC and SPD
SPD and SPC function as a serial interface where SPD is bi-directional data and SPC is an input only serial clock. In
the reference design, SPD and SPC pins are pulled up to +1.8V ~ +3.3V with 6.8 kΩ resistors as shown in Figure 7.
• SPCM and SPDM
SPCM and SPDM can automatically load firmware from external EEPROM . In the reference design, SPDM and
SPCM pins are pulled up to +3.0V ~ +3.5Vwith 6.8 KΩ resistors as shown in Figure 7.
Note: CH9904 hard wire address should be 57h.
• DDC_SC and DDC_SD
DDC_SC and DDC_SD are used to interface with the DDC of VGA. This DDC pair needs to be pulled up to 5V
through resistors (Refer to Figure 7).
VCC3_3
R5
R6
6.8K
6.8K
DDC_SC and DDC_SD connect to VGA connector.
The resistor(R3and R4) value according to the capactive Loading.
It is highly recommended to add diode(SM5817) to prevent back
driver from TV or Monitor in VDD5
SPCM and SPDM for autoload
Figure 7: Serial Port Interface: SPCM, SPDM and SPC, SPD pins of CH7034B
2.5
Input Pins
6
VCC3_3
R1
R2
6.8K
VDD5
D14
SM5817
VCC3_3
R7
6.8K
U2
1
8
GP1
VCC
2
7
R9 10K
GP2
WE
3
6
GP3
SPC
4
5
GND
SPD
CH9904
6.8K
54
SPC
55
SPD
VDD5_d
R3
R4
1.8K
1.8K
63
VCC3_3
64
R8
R9
6.8K
6.8K
72
SPCM
69
SPDM
C1
0.1uF
206-1000-013
AN-B013
U1
SPC
SPD
CH7034
DDC_SC
QFN
DDC_SD
SPCM
SPDM
Rev1.4,
06/30/2020