digitalview IE-1000 Посібник - Сторінка 11

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CN3 – LVDS signal output connector : JST BM50B-SRDS (Matching type : SHDR-50V-S-B)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CN4 – LVDS signal output connector : JST BM40B-SRDS (Matching type : SHDR-40V-S-B)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Specifications subject to change without notice
© Digital View Ltd – Doc Ver 1.4: 26 March, 2009 (IE-1000 -2X manual.doc)
SYMBOL
LVDS_OUT1_B0+
LVDS_OUT1_B0-
LVDS_OUT1_B1+
LVDS_OUT1_B1-
OP1
OP2
LVDS_OUT1_B2+
LVDS_OUT1_B2-
LVDS_OUT1_BC+
LVDS_OUT1_BC-
LVDS_OUT1_B3+
LVDS_OUT1_B3-
LVDS_OUT1_B4+
LVDS_OUT1_B4-
LVDS_OUT1_A0+
LVDS_OUT1_A0-
LVDS_OUT1_A1+
LVDS_OUT1_A1-
LVDS_OUT1_A2+
LVDS_OUT1_A2-
OP3
OP4
LVDS_OUT1_AC+
LVDS_OUT1_AC-
LVDS_OUT1_A3+
LVDS_OUT1_A3-
GND
GND
LVDS_OUT1_A4+
LVDS_OUT1_A4-
GND
GND
GND
GND
GND
GND
VLCD_LV
VLCD_LV
VLCD_LV
VLCD_LV
VLCD_LV
VLCD_LV
NC
VLCD_HV
VLCD_HV
VLCD_HV
VLCD_HV
VLCD_HV
VLCD_HV
VLCD_HV
SYMBOL
LVDS_OUT2_B0+
LVDS_OUT2_B0-
LVDS_OUT2_B1+
LVDS_OUT2_B1-
OP1
OP2
LVDS_OUT2_B2+
LVDS_OUT2_B2-
LVDS_OUT2_BC+
LVDS_OUT2_BC-
LVDS_OUT2_B3+
LVDS_OUT2_B3-
LVDS_OUT2_B4+
LVDS_OUT2_B4-
DESCRIPTION
Positive differential LVDS data bit B0
Negative differential LVDS data bit B0
Positive differential LVDS data bit B1
Negative differential LVDS data bit B1
Reserved
Reserved
Positive differential LVDS data bit B2
Negative differential LVDS data bit B2
Positive LVDS clock for A channel
Negative LVDS clock for A channel
Positive differential LVDS data bit B3
Negative differential LVDS data bit B3
Positive differential LVDS data bit B4
Negative differential LVDS data bit B4
Positive differential LVDS data bit A0
Negative differential LVDS data bit A0
Positive differential LVDS data bit A1
Negative differential LVDS data bit A1
Positive differential LVDS data bit A2
Negative differential LVDS data bit A2
Reserved
Reserved
Positive LVDS clock for A channel
Negative LVDS clock for A channel
Positive differential LVDS data bit A3
Negative differential LVDS data bit A3
Ground
Ground
Positive differential LVDS data bit A4
Negative differential LVDS data bit A4
Ground
Ground
Ground
Ground
Ground
Ground
Panel power supply (3,3V/5V) from front end controller
Panel power supply (3,3V/5V) from front end controller
Panel power supply (3,3V/5V) from front end controller
Panel power supply (3,3V/5V) from front end controller
Panel power supply (3,3V/5V) from front end controller
Panel power supply (3,3V/5V) from front end controller
No connection
Panel power supply (+12V/18V) from front end controller
Panel power supply (+12V/18V) from front end controller
Panel power supply (+12V/18V) from front end controller
Panel power supply (+12V/18V) from front end controller
Panel power supply (+12V/18V) from front end controller
Panel power supply (+12V/18V) from front end controller
Panel power supply (+12V/18V) from front end controller
DESCRIPTION
Positive differential LVDS data bit B0
Negative differential LVDS data bit B0
Positive differential LVDS data bit B1
Negative differential LVDS data bit B1
Reserved
Reserved
Positive differential LVDS data bit B2
Negative differential LVDS data bit B2
Positive LVDS clock for A channel
Negative LVDS clock for A channel
Positive differential LVDS data bit B3
Negative differential LVDS data bit B3
Positive differential LVDS data bit B4
Negative differential LVDS data bit B4
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