Cisco UCS C480 M5 Посібник - Сторінка 7
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DCPMM Guidelines
DCPMMs require second generation Intel Xeon Scalable Family processors. First generation Xeon Scalable
processors do not support DCPMMs.
All installed DCPMMs must be the same size. Mixing DCPMMs of different capacities is not supported.
DCPMMs and DIMMs must be populated as shown in
CPU, as shown).
Table 2 2
nd
Generation Intel
socket)
DIMM
to
DCPMM
Count
Channel 2
F2
F1
6 to 2
DIMM
6 to 4
DIMM
6 to 6
DCPMM
DIMM
DIMM
to
DCPMM
Count
Channel 2
M2
M1
6 to 2
DIMM
6 to 4
DIMM
6 to 6
DCPMM
DIMM
DIMM
to
DCPMM
Count
Channel 2
F2
F1
6 to 2
DIMM
6 to 4
DIMM
6 to 6
DCPMM
DIMM
Cisco UCS C480 M5 Memory Guide
®
Xeon
®
Scalable Processor DIMM and DCPMM
iMC1
Channel 1
Channel 0
E2
E1
D2
DIMM
DCPMM
DCPMM
DIMM
DCPMM
DCPMM
DIMM
DCPMM
iMC1
Channel 1
Channel 0
L2
L1
K2
DIMM
DCPMM
DCPMM
DIMM
DCPMM
DCPMM
DIMM
DCPMM
iMC1
Channel 1
Channel 0
E2
E1
D2
DIMM
DCPMM
DCPMM
DIMM
DCPMM
DCPMM
DIMM
DCPMM
Table 2
(6 DIMMs per CPU with 2, 4, or 6 DCPMMs per
CPU 1 (lower bay)
Channel 2
D1
C2
C1
DIMM
DIMM
DIMM
DIMM
DIMM
DCPMM
DIMM
CPU 2 (lower bay)
Channel 2
K1
J2
J1
DIMM
DIMM
DIMM
DIMM
DIMM
DCPMM
DIMM
CPU 3 (upper bay)
Channel 2
D1
C2
C1
DIMM
DIMM
DIMM
DIMM
DIMM
DCPMM
DIMM
Memory Configurations and Modes
1
Physical Configurations (quad
iMC0
Channel 1
Channel 0
B2
B1
A2
DIMM
DCPMM
DCPMM
DIMM
DCPMM
DCPMM
DIMM
DCPMM
iMC0
Channel 1
Channel 0
H2
H1
G2
DIMM
DCPMM
DCPMM
DIMM
DCPMM
DCPMM
DIMM
DCPMM
iMC0
Channel 1
Channel 0
B2
B1
A2
DIMM
DCPMM
DCPMM
DIMM
DCPMM
DCPMM
DIMM
DCPMM
A1
DIMM
DIMM
DIMM
G1
DIMM
DIMM
DIMM
A1
DIMM
DIMM
DIMM
7