Yamaha HTR-5740 Посібник з експлуатації - Сторінка 26
Переглянути онлайн або завантажити pdf Посібник з експлуатації для Приймач Yamaha HTR-5740. Yamaha HTR-5740 39 сторінок. Av receiver/av amplifier
- 1. Contents
- 2. Service Manual
- 3. Set Menu Table
- 4. Internal View
- 5. Block Diagram
- 6. Printed Circuit Board (Foil Side)
- 7. Schematic Diagram
- 8. Schematic Diagram (Operation)
- 9. Schematic Diagram (Main)
- 10. Schematic Diagram (Power)
- 11. Schematic Diagram (Subtrans)
- 12. Schematic Diagram (Video)
- 13. Exploded View
A
B
C
SCHEMATIC DIAGRAM (DSP)
1
4.9
4.9
0
4.9
4.9
3.6
3.6
4.9
4.9
3.6
0
2.6
0
0
0
3.6
0
3.9
2
0
0
0
0
4.9
0
0
0
4.9
4.9
0
0
4.9
0
0.2
0
DUTY
4.9
CORRECTOR
3.9
0
4.9
3
0
0
0.1
3.9
0
DIR
3.4
4.9
0.2
0.1
3.9
0.3
0
0.1
0.4
3.4
0
4
2.6
0.4
3.1
4.8
0
0.1
DUTY
CORRECTOR
5
4.9
0.1
0.1
4.9
0.1
0.1
3.3
0.1
0.1
0.1
0.1
0.1
0.1
3.3
0.1
0.1
0.1
3.3
0.1
3.3
0.1
0.1
0.1
3.3
0.1
0.1
0.1
0.1
6
0.1
0.1
0.1
0.1
0
0
0.1
0
1.2
1M SRAM
1.2
3.4
0
0
3.3
3.3
3.3
1.2
1.2
0
0
3.3
0
7
3.3
3.4
1.2
1.2
0
0
0
3.4
3.4
3.4
8
IC1 : MM74HCU04SJX
IC3: TC74HCT00AF
IC2: LC89057W-VF4D-E
Quad 2-Input Nand Gate
Hex Inverters
Digital Audio Interface Transceiver
9
1A
1
14
Vcc
A1
1
14
VCC
1B
2
13
4B
Y1
2
13
A6
1Y
3
12
4A
2A
4
11
4Y
RXOUT
1
A2
3
12
Y6
2B
5
10
3B
RX0
2
2Y
6
9
3A
Y2
4
11
A5
GND
7
8
3Y
3
RX1
A3
5
10
Y5
RX2
4
RX3
5
Y3
6
9
A4
RX4
8
GND
7
8
Y4
RX5/VI
9
RX6/UI
10
LPF
13
TMCK/PIO0
44
TBCK/PIO1
45
10
TLRCK/PIO2
46
TDATA/PIO3
47
TXO/PIOEN
48
D
E
F
RX-V550/HTR-5750
Reference No.
U, C, R, T, K, A, B, G, L, E
memo
s1
R57
4.7K
AAC
s2
MOUNT
Digital Out MD/CDR In
s3
MOUNT
COAX
RX-V450/HTR-5740/DSP-AX450
Reference No.
J
U, C, R, T, K, A, B, G, L, E
memo
s1
R57
NOT USED
4.7K
AAC
s2
MOUNT
NO MOUNT
Digital Out MD/CDR In
s3
NO MOUNT
MOUNT
COAX
3.0
1.2
4.9
2.5
3.4
4.9
1.2
2.5
3.4
3.4
4.9
0
0
0
Point: Pin 28 of IC2
3.3
0
0
0
0
3.4
1.5
1.6
1.6
3.4
0
0.1
1.2
1.2
0
3.3
0.1
0.1
0.1
1.2
1.2
0
0
3.4
0.1
0
0
1.2
1.2
MAIN
0
0
DECODER
3.4
0.7
0.7
0
0
1.2
1.3
1.7
1.7
IC4: NJM2904M
Dual OP-Amp
EMPHA/UO
AUDIO/VO
INT
CL
CE
CI
XMODE
32
33
35
48
39
38
41
Microcontroller
Cbit, Ubit
37
DO
Q2
Q3
I/F
–
Q1
Q4
36
RERR
INPUTS
Input
Demodulation
Data
21
RDATA
Selector
&
+
Selector
Lock detect
SDIN
24
Q8
Q9
16
RMCK
PLL
17
RBCK
Clock
20
RLRCK
Selector
22
SBCK
Modulation
1/N
&
SLRCK
23
Parallel Port
29
28
27
34
XIN
XOUT XMCK CKST
G
H
RX-V550: Page 77
L10
HTR-5750, RX-V450, HTR-5740, DSP-AX450: Page 79
M10
HTR-5750, RX-V450, HTR-5740, DSP-AX450: Page 78
to FUNCTION (2)
SELECTOR
4M DRAM
0
2.5
0.7
0.7
1.0
1.0
1.0
1.0
0.7
0.7
3.4
4.8
0.7
0
0.7
3.3
3.4
3.3
1.7
4.8
1.7
1.7
1.7
POST
0.8
0
PROCESSOR
0
0
0.7
1.5
0.7
0.8
1.2
1.5
1.3
1.9
2.5
0
IC6: CY62128BLL-70SCT
Memory
V–
Q6
Q5
Q7
OUTPUT
Q13
I/O
0
Q11
INPUT BUFFER
Q12
Q10
I/O
1
A
0
A
1
I/O
2
A
2
A
3
A
4
I/O
3
A
512 x 256 x 8
5
ARRAY
A
6
I/O
4
A
7
A
8
I/O
5
I/O
6
POWER
COLUMN
CE
1
DOWN
DECODER
CE
2
I/O
7
WE
OE
I
J
K
RX-V550: Page 76
H2
H2
to FUNCTION (1)
3.4
3.4
0
0
5.0
5.0
1.7
1.5
1.7
0
1.7
2.5
0
1.7
11.8
1.7
2.5
0
-0.1
0
1.7
-0.1
2.5
2.5
-0.1
-0.1
-0.1
0
-11.6
0
CENTER
0
11.8
0
0
0
0
0
0
0
2.5
-11.6
A/D
2.5
0.1
1.7
0
1.7
2.5
1.5
2.5
SURROUND L
0.8
-0.1
1.5
2.5
11.8
1.9
2.5
0
-0.1
-0.1
0
2.5
-0.1
-0.1
-0.1
-11.6
FRONT L
-0.1
11.8
-0.1
-0.1
-0.1
-0.1
-11.6
-0.1
IC7: YSS930-SZ
Programmable 32 bit DSP
XO
XI
/CS
CPO
SDI INTERFACE
SO
SI
DSP Internal Clock CK
(30.72 ~ 40.96 MHz)
SCK
DATA RAM
VSS
1
75
VDD2
RAMD15-0
32 bit x 1024 word
IOPORT19-0
MPLOAD
XO
2
74
RAMA10
CASN
XI
3
73
RAMA9
RASN
IOPORT0
4
72
RAMA3
IOPORT1
5
71
RAMA4
RAMWEN
IOPORT2
6
70
RAMA2
RAMOEN
IOPORT3
7
69
RAMA5
RAMA17-0
IOPORT4
8
68
VDD1
IOPORT5
9
67
RAMA1
IOPORT6
10
66
RAMA6
IOPORT7
11
65
RAMA0
AVSS
12
64
RAMA7
32 bit DSP CORE
CPO
13
63
RAMA8
AVDD
14
62
RASN
VDD1
15
61
RAMOEN
(NC)
16
60
RAMWEN
IOPORT8
17
59
CASN
IOPORT9
18
58
RAMD15
OVF
IOPORT10
19
57
RAMD11
END
IOPORT11
20
56
RAMD13
IOPORT12
21
55
VDD1
IOPORT13
22
54
RAMD12
IOPORT14
23
53
RAMD11
IOPORT15
24
52
RAMD10
VDD2
25
51
VSS
SDBCKO
BCKOP
SDWCKO
SDO INTERFACE
WCKOP
ZEROF7R-0L
L
M
N
RX-V550/HTR-5750/RX-V450/HTR-5740/DSP-AX450
IC8: MSM514260E-60JS
4Mbit DRAM
WE
OE
13
27
Timing
RAS
14
Generator
I/O
Controller
LCAS
29
Output
8
UCAS
28
I/O
8
Buffers
Controller
DQ1~DQ8
Column
9
Address
9
Column Decoders
Input
8
8
Buffers
Buffers
I/O
Internal
Sense Amplifiers
16
16
Refresh
Selector
A0~A8
Address
Control Clock
Counter
Input
8
8
Buffers
Row
Row
9
Address
9
Word
Deco-
Memory
DQ9~DQ16
Buffers
Drivers
Cells
ders
Output
8
8
Buffers
VCC
20
On Chip
VBB Generator
VSS
21
IC10: SN74LV245APWR
IC12: PQ025EZ5MZP
Octal Bus Transceiver with 3-state Outputs
Regulator
Vin
1
3
Vo
DIR
1
20
Vcc
A1
2
19
OE
2
Vc
5
3
18
GND
A2
B1
A3
4
17
B2
A4
5
16
B3
A5
6
15
B4
A6
7
14
B5
8
13
A7
B6
A8
9
12
B7
GND
10
11
B8
IC11: µPC29M33T-E1
Voltage Regulator
INPUT
1
Safety Drive
Limiter
Amp.
3
OUTPUT
Excessive Electric
Current Protection
2
GND
IC13: PQ012FZ01ZP
IC14: 74VHC157MTCX
Voltage Regulator
Quad 2-Input Multiplexer
Vin
1
3
Vo
1
S
Specific IC
VB
2
4
Vc
E
15
5
GND
I1d
10
9
Zd
I0d
11
IC18: µPC4570G2
I1c
13
12
Zc
IC19~21: NJM2068MD
Dual OP-Amp
I0c
14
I1b
6
7
Zb
OUT
1
1
8
+V
CC
I0b
5
–IN
2
7
OUT
1
2
I1a
3
+
–
+
–
4
Za
+IN
3
6
–IN
I0a
2
1
2
–V
CC
4
5
+IN
2
IC22: SN74AHCT08PWR
IC16: AK4628VQ
Quad 2-Input And Gate
192kHz 24Bit 8-channel CODEC
Audio
1A
1
14
Vcc
LIN
31
ADC
HPF
I/F
1B
2
13
4B
RIN
32
ADC
HPF
1Y
3
12
4A
LOUT1
27
LPF
DAC
DATT
MCLK
39
MCLK
2A
4
11
4Y
LRCK
5
LRCK
ROUT1
28
LPF
DAC
DATT
BICK
4
BICK
2B
5
10
3B
DAUX
10
2Y
6
9
3A
LOUT2
25
LPF
DAC
DATT
Format
Converter
GND
7
8
3Y
ROUT2
LPF
DAC
DATT
26
SDOUT
SDOS
LOUT3
23
LPF
DAC
DATT
1
9
SDTO
ROUT3
24
LPF
DAC
DATT
SDIN1
6
SDTI1
SDIN2
7
SDTI2
SDIN3
8
SDTI3
LOUT4
21
LPF
DAC
DATT
SDIN4
12
SDTI4
ROUT4
LPF
DAC
DATT
22
AK4628
SDOS
1
33
DZF2/OVF
I2C
2
32
RIN
SMUTE
3
31
LIN
BICK
4
30
NC
LRCK
5
29
MASTER
SDTI1
6
28
ROUT1
SDTI2
7
27
LOUT1
SDTI3
8
26
ROUT2
SDTO
9
25
LOUT2
DAUX
10
24
ROUT3
DFS0
11
23
LOUT3
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
s
75