Cypress CY3274 Примітки щодо застосування - Сторінка 14
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Друкувати сторінку3.3
Signal Path Component Requirements
The chip bead L2 is designed specifically for powerline applications and provides a low DC resistance (0.02 ) and
high current handling capability (3 A). Its impedance curve is similar to that of a 0.4 H inductor. The transmit
capacitors C10 and C30 should be sized so that they match the impedance of the inductor as closely as possible.
This reduces the transmit impedance, which increases the driving distance of the system. In this case, C10 and C30
are each 10 F, which yields an equivalent capacitance of 5 F. At 132 kHz, the impedance of this equivalent
capacitor matches the inductor to within 0.1 . Capacitor C30 must also be rated to be above the maximum voltage
on the powerline.
The opamp U1 used in the transit amplifier section must provide both high speed to minimize crossover distortion,
and relatively high output currents to drive the output transistors.
3.4
Power Supply
This section describes the power supply design for low voltage boards. The schematic of the power supply is shown
in
Figure 9
and the BOM for the power supply is listed in
Inductor L4 provides high impedance to the powerline so that the power supply does not load the PLC signal. It
should be rated to ≥ 200 mA.
Resistor R2 limits in-rush current. It should be rated to ≥ 1 W.
D9 protects the circuit from voltage transients and D10 rectifies the voltage when AC power is present.
Regulator U7 provides a 5 V output, which is used for the PLC device and the transmit amplifier.
The 100 µF electrolytic capacitor C24, along with a 10 µF tantalum capacitor and two 0.1 µF ceramic capacitors
provide the necessary decoupling for the PLC device, considering the 5 V supply is shared with the transmit amplifier.
www.cypress.com
Figure 9. Power Supply Circuit while designing Low Voltage PLC Board
Document No. 001-55427 Rev. *E
Cypress Powerline Communication Board Design Analysis
Table
6.
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