Cypress Semiconductor CY62138FV30 Технічна специфікація - Сторінка 13
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Document History Page
Document Title: CY62138FV30 MoBL
Document Number: 001-08029
Issue
REV.
ECN NO.
Date
**
463660
See ECN
*A
467351
See ECN
*B
566724
See ECN
*C
797956
See ECN
*D
809101
See ECN
*E
940341
See ECN
Document #: 001-08029 Rev. *E
®
, 2-Mbit (256K x 8) Static RAM
Orig. of
Change
NXR
New data sheet
NXR
Added 32-pin TSOP II package, 32 pin TSOP I and 32 pin STSOP packages
Changed ball A3 from NC to CE
NXR
Converted from Preliminary to Final
Corrected typo in 32 pin TSOP II pin configuration diagram on page #2 (changed
pin 24 from CE
to OE and pin 22 from CE to CE
1
Changed the I
CC(max)
Changed the I
SB2(typ)
Changed the I
SB2(max)
Changed the I
CCDR(typ)
µA to 4 µA
VKN
Added 32-pin SOIC package
Updated VIL spec for SOIC, TSOP-II, TSOP-I, and STSOP packages on Electrical
characteristics table
VKN
Corrected typo in the Ordering Information table
VKN
Added footnote #7 related to I
CY62138FV30 MoBL
Description of Change
in 36-ball FBGA pin out
2
)
1
value from 2.25 mA to 2.5 mA for test condition f=1 MHz
value from 0.5 µA to 1 µA
value from 2.5 µA to 5 µA
value from 0.5 µA to 1 µA and I
and I
SB2
CCDR
®
value from 2.5
CCDR(max)
Page 13 of 13
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