Cypress Semiconductor CY7B9910 Технічна специфікація - Сторінка 6

Переглянути онлайн або завантажити pdf Технічна специфікація для Комп'ютерне обладнання Cypress Semiconductor CY7B9910. Cypress Semiconductor CY7B9910 12 сторінок. Cypress low skew clock buffer specification sheet

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Parameter
f
Operating Clock
NOM
Frequency in MHz
t
REF Pulse Width HIGH
RPWH
t
REF Pulse Width LOW
RPWL
t
Zero Output Skew (All Outputs)
SKEW
t
Device-to-Device Skew
DEV
t
Propagation Delay, REF Rise to FB Rise
PD
t
Output Duty Cycle Variation
ODCV
t
Output Rise Time
ORISE
t
Output Fall Time
OFALL
t
PLL Lock Time
LOCK
t
Cycle-to-Cycle Output Jitter Peak to Peak
JR
Notes
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
10. Applies to REF and FB inputs only.
11. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
12. Except as noted, all CY7B9920–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load.
13. tSKEW is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50Ω to
2.06V (CY7B9910) or VCC/2 (CY7B9920).
14. tSKEW is defined as the skew between outputs.
15. tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (VCC, ambient temperature, air flow, and
so on).
16. tODCV is the deviation of the output from a 50% duty cycle.
17. Specified with outputs loaded with 30 pF for the CY7B99X0–2 and –5 devices and 50 pF for the CY7B99X0–7 devices. Devices are terminated through 50Ω to
2.06V (CY7B9910) or VCC/2 (CY7B9920).
18. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B9910 or 0.8VCC and 0.2VCC for the CY7B9920.
19. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This
parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07135 Rev. *B
Description
[1, 2]
FS = LOW
[1, 2]
FS = MID
[1, 2, 3]
FS = HIGH
[13, 14]
[8, 15]
[16]
[17, 18
[17, 18]
[19]
[8]
[8]
RMS
CY7B9910–5
Min
Typ
Max
15
30
15
25
50
25
40
80
40
5.0
5.0
5.0
5.0
0.25
0.5
1.0
–0.5
0.0
+0.5
–0.5
–1.0
0.0
+1.0
–1.0
0.15
1.0
1.5
0.5
0.15
1.0
1.5
0.5
0.5
200
25
CY7B9910
CY7B9920
CY7B9920–5
Min
Typ
Max
Unit
30
MHz
50
[12]
80
ns
ns
0.25
0.5
ns
1.0
ns
0.0
+0.5
ns
0.0
+1.0
ns
2.0
3.0
ns
2.0
3.0
ns
0.5
ms
200
ps
25
ps
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