Cypress Semiconductor CY7C1297H Технічна специфікація - Сторінка 9

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Switching Characteristics

Parameter
t
V
(Typical) to the First Access
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid after CLK Rise
CDV
t
Data Output Hold after CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
OE LOW to Output Valid
t
OEV
OE LOW to Output Low-Z
t
OELZ
OE HIGH to Output High-Z
t
OEHZ
Set-up Times
t
Address Set-up before CLK Rise
AS
ADSP, ADSC Set-up before CLK Rise
t
ADS
ADV Set-up before CLK Rise
t
ADVS
t
GW, BWE, BW
WES
t
Data Input Set-up before CLK Rise
DS
t
Chip Enable Set-up
CES
Hold Times
t
Address Hold after CLK Rise
AH
ADSP, ADSC Hold after CLK Rise
t
ADH
t
GW, BWE, BW
WEH
ADV Hold after CLK Rise
t
ADVH
t
Data Input Hold after CLK Rise
DH
t
Chip Enable Hold after CLK Rise
CEH
Notes:
10. Timing reference level is 1.5V when V
11. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
12. This part has a voltage regulator internally; t
can be initiated.
13. t
, t
,t
, and t
are specified with AC test conditions shown in (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
14. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
Document #: 38-05669 Rev. *B
Over the Operating Range
Description
[12]
[13, 14, 15]
[13, 14, 15]
[13, 14, 15]
[13, 14, 15]
Set-up before CLK Rise
[A:B]
Hold after CLK Rise
[A:B]
= 3.3V and is 1.25V when VDDQ = 2.5V.
DDQ
is the time that the power needs to be supplied above V
POWER
is less than t
and t
OEHZ
OELZ
CHZ
[10, 11]
133 MHz
Min.
1
7.5
2.5
2.5
2.0
0
0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
(minimum) initially before a Read or Write operation
DD
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
CY7C1297H
100 MHz
Max.
Min.
Max.
Unit
1
ms
10.0
ns
4.0
ns
4.0
ns
6.5
8.0
ns
2.0
ns
0
ns
3.5
3.5
ns
3.5
3.5
ns
0
ns
3.5
3.5
ns
2.0
ns
2.0
ns
2.0
ns
2.0
ns
2.0
ns
2.0
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
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