Cypress Semiconductor CY7C1306BV25 Технічна специфікація - Сторінка 19
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Document History Page
Document Title: CY7C1303BV25/CY7C1306BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture
Document Number: 38-05627
REV.
ECN NO.
Issue Date
**
253010
See ECN
*A
436864
See ECN
Document #: 38-05627 Rev. *A
Orig. of
Change
SYT
New Data Sheet
NXR
Converted from Preliminary to Final.
Removed 133 MHz & 100 MHz from product offering.
Included the Industrial Operating Range.
Changed C/C Description in the Features Section & Pin Description Table.
Changed t
from 100 ns to 50 ns, changed t
TCYC
and changed t
and t
TH
Characteristics table
Modified the ZQ pin definition as follows:
Alternately, this pin can be connected directly to V
minimum impedance mode
Included Maximum Ratings for Supply Voltage on V
Changed the Maximum Ratings for DC Input Voltage from V
Modified the Description of I
Current on page # 15.
Modified test condition in note# 13 from V
Updated the Ordering Information table and replaced the Package Name
Column with Package Diagram.
CY7C1303BV25
CY7C1306BV25
Description of Change
from 10 MHz to 20 MHz
TF
from 40 ns to 20 ns in TAP AC Switching
TL
DDQ
from Input Load current to Input Leakage
X
< V
DDQ
DD
, which enables the
Relative to GND
DDQ
to V
DDQ
DD.
≤ V
to V
DDQ
DD
Page 19 of 19
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