Cypress Semiconductor CY7C1329H Технічна специфікація
Переглянути онлайн або завантажити pdf Технічна специфікація для Комп'ютерне обладнання Cypress Semiconductor CY7C1329H. Cypress Semiconductor CY7C1329H 17 сторінок. 2-mbit (64k x 32) pipelined sync sram
Друкувати сторінкуFeatures
• Registered inputs and outputs for pipelined operation
• 64K × 32 common I/O architecture
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• "ZZ" Sleep Mode Option
Logic Block Diagram
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
D
WRITE REGISTER
BW
C
WRITE REGISTER
BW
B
WRITE REGISTER
BW
A
WRITE REGISTER
BWE
GW
CE
1
CE
2
CE
3
OE
SLEEP
ZZ
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05673 Rev. *B
2-Mbit (64K x 32) Pipelined Sync SRAM
®
ADDRESS
REGISTER
2
A
[1:0]
Q1
BURST
COUNTER
AND
CLR
Q0
LOGIC
DQ
D
BYTE
DQ
C
BYTE
DQ
B
BYTE
DQ
A
BYTE
ENABLE
PIPELINED
REGISTER
ENABLE
•
198 Champion Court
Functional Description
The CY7C1329H SRAM integrates 64K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE
1
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
and BWE), and Global Write (GW). Asynchronous
[A:D]
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte
Write operations (see Pin Descriptions and Truth Table for
further details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1329H operates from a +3.3V core power supply
while all outputs operate with either a +2.5V or +3.3V supply.
All
inputs
and
JESD8-5-compatible.
DQ
D
BYTE
WRITE DRIVER
DQ
C
BYTE
WRITE DRIVER
MEMORY
SENSE
ARRAY
AMPS
DQ
B
BYTE
WRITE DRIVER
DQ
A
BYTE
WRITE DRIVER
,
•
San Jose
CA 95134-1709
CY7C1329H
[1]
and CE
), Burst
2
3
outputs
are
JEDEC-standard
OUTPUT
OUTPUT
BUFFERS
REGISTERS
E
INPUT
REGISTERS
•
408-943-2600
Revised March 22, 2006
D Q s
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