Cypress Semiconductor CY7C1332AV25 Технічна специфікація - Сторінка 5

Переглянути онлайн або завантажити pdf Технічна специфікація для Комп'ютерне обладнання Cypress Semiconductor CY7C1332AV25. Cypress Semiconductor CY7C1332AV25 19 сторінок. Cypress 18-mbit (512k x 36/1mbit x 18) pipelined register-register late write specification sheet

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guaranteed. The device must be deselected prior to entering
the "sleep" mode. CE must remain inactive for the duration of
t
after the ZZ input returns LOW.
ZZREC
Cycle Description Truth Table
Operation Address Used CE
Deselected External
Begin Read External
Begin Write External
Sleep Mode
-
ZZ Mode Electrical Characteristics
Parameter
I
Snooze mode standby current
DDZZ
t
Device operation to ZZ
ZZS
t
ZZ recovery time
ZZREC
Write Cycle Descriptions
Function (CY7C1330AV25)
Read
Write Byte 0 – DQ
a
Write Byte 1 – DQ
b
Write Bytes 1, 0
Write Byte 2 – DQ
c
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 – DQ
d
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
Abort Write All Bytes
Write Cycle Descriptions
Function (CY7C1332AV25)
Read
Write Byte 0 – DQ
a
Write Byte 1 – DQ
b
Write All Bytes
Abort Write All Bytes
Notes:
1. X = "Don't Care," 1 = Logic HIGH, 0 = Logic LOW. BWS x = 0 signifies at least one Byte Write Select is active, BWS x = Valid signifies that the desired byte write
selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS x . See Write Cycle Description table for details.
3. The DQ pins are controlled by the current cycle and the OE signal.
4. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
5. OE assumed LOW.
Document No: 001-07844 Rev. *A
PRELIMINARY
[1, 2, 3, 4, 5]
WE BWS
CLK ZZ
x
1
X
X
L-H
0
I/Os tri-state following next recognized clock.
0
1
X
L-H
0
Address latched. Data driven out on the next rising edge of the clock.
0
0
Valid
L-H
0
Address latched, data presented to the SRAM on the next rising
edge of the clock.
X
X
X
X
1
Power down mode.
Description
[1, 2]
WE
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[1, 2]
WE
Comments
Test Conditions
ZZ > V
IH
ZZ > V
IH
ZZ < V
IL
BW
BW
d
c
X
X
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
BW
b
1
X
0
1
0
0
0
0
0
1
CY7C1330AV25
CY7C1332AV25
Min.
Max.
Unit
128
mA
2t
ns
CYC
2t
ns
CYC
BW
BW
b
a
X
X
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
BW
a
X
0
1
0
1
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