Cypress Semiconductor CY7C1333H Технічна специфікація

Переглянути онлайн або завантажити pdf Технічна специфікація для Комп'ютерне обладнання Cypress Semiconductor CY7C1333H. Cypress Semiconductor CY7C1333H 13 сторінок. Cypress 2-mbit (64k x 32) flow-through sram with nobl architecture specification sheet

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Features
• Can support up to 133-MHz bus operations with zero
wait states.
— Data is transferred on every clock.
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 64K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 8.0 ns (for 100-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes Offered in Lead-Free
• Asynchronous Output Enable
• Offered in Lead-Free JEDEC-standard 100 TQFP
package
• Burst Capability—linear or interleaved burst order
Logic Block Diagram
A0, A1, A
MODE
CE
CLK
C
CEN
ADV/LD
BW
A
BW
B
BW
C
BW
D
WE
OE
CE1
CE2
CE3
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-00209 Rev. **
PRELIMINARY
2-Mbit (64K x 32) Flow-Through SRAM
Functional Description
The CY7C1333H is a 3.3V, 64K x 32 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1333H is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
ADDRESS
A1
REGISTER
D1
A0
D0
BURST
ADV/LD
LOGIC
C
WRITE ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
Control
•
3901 North First Street
with NoBL™ Architecture
• Low standby power
) and a Write Enable (WE) input. All writes are
[A:D]
A1'
Q1
A0'
Q0
S
E
N
S
MEMORY
WRITE
E
ARRAY
DRIVERS
A
M
P
S
INPUT
E
REGISTER
,
•
San Jose
CA 95134
CY7C1333H
[1]
, CE
, CE
) and an
1
2
3
O
U
T
P
D
U
A
T
T
A
B
U
S
DQs
F
T
F
E
E
E
R
R
S
I
N
E
G
•
408-943-2600
Revised April 11, 2005
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